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PDF AD9561 Data sheet ( Hoja de datos )
| Número de pieza | AD9561 | |
| Descripción | Pulse Width Modulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
60 MHz Pulse Rate
8-Bit Resolution
Center, Left or Right Justify
Low Power: 700 mW typical
Minimum Pulse Width: <5 ns
Maximum PW: 100 % Full-scale
APPLICATIONS
Laser Printers
Digital Copiers
Color Copiers
Pulse Width Modulator
AD9561
FUNCTIONAL BLOCK DIAGRAM
AD9561
CLOCK
RSET
CAL IN
INTERNAL
TIMING
RAMP
CAL
OUT
RAMP
REF
CAL
DAC
8-BIT
DATA
SEM/DEM
LEM/TEM
RETRACE
LL
AA
TT
CC
HH
DAC
OUTPUT
LOGIC
PWM
OUT
CAL
OUT
GENERAL DESCRIPTION
The AD9561 is a second generation high speed, digitally
programmable pulse width modulator (PWM). Output pulse
width is proportional to an 8-bit DATA input value. Two
additional control inputs determine if the pulse is placed at the
beginning, middle or end of the clock period. Pulse width and
placement can be changed every clock cycle up to 60 MHz.
Pulse width modulation is a well proven method for controlling
gray scale and resolution enhancement in scanning laser print
engines. Modulating pulse width provides the most cost
effective method for continuous tone reproduction and resolu-
tion enhancement in low-to-moderate cost scanning electro-
photographic systems.
The AD9561 uses precision analog circuits to control dot size
so that near-photographic quality images are practical without
the high frequency clock signals required by all digital approaches.
The AD9561 has improved features and performance over its
predecessor, the AD9560. An improved ramp topology enables
control of pulse width through 100% of the dot clock period as
opposed to 95% for the AD9560. This enables smooth transi-
tion across dot boundaries for line screen applications.
Additionally, input data setup and hold time are symmetrical at
2 ns each, simplifying interface to the system bus.
Finally, chip design and pinout are optimized to decrease
sensitivity of analog circuits to digital coupling. (See layout
section for detailed recommendations for optimum results.)
Inputs are TTL or CMOS compatible, and outputs are CMOS
compatible. The AD9561JR is packaged in a 28-lead plastic
SOIC. It is rated over the commercial temperature range, 0°C
to +70°C.
HIGHLIGHTS
1. 60 MHz native printer clock rate.
2. Single +5 V power supply.
3. On-chip Autocalibration.
4. Pulse placement flexibility.
5. High resolution: 256 pulse widths.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
AD9561
Pulse Pattern Example
Figure 1 at the top of the previous page illustrates the PWM
OUT of the AD9561 with various DATA and CONTROL
inputs. The DATA format is Binary. In the Pulse Pattern
Example, the Hexadecimal format is used, i.e., FFH represents
decimal 255.
The top line shows the CLOCK; the second shows DATA and
CONTROL inputs, which are latched on the rising edge of
CLOCK. The third line shows the resulting pulse.
The AD9561 DATA and CONTROL inputs are double
latched. The OUTPUT pulse labeled “Pulse N” results from
DATA and CONTROL values latched in by the first CLOCK,
illustrating the one CLOCK period timing delay.
The CONTROL value number for pulse one is shown as xx.
This means the value is not important because a 100% pulse
will be output for any CONTROL value for DATA value 255 or
FFH. Likewise, OUTPUT Pulse N is noted as 100% DNC (do
not care), also noting that CONTROL value is unimportant.
The fourth DATA/CONTROL value is C0/0X. This indicates
that the level for LEM/TEM is unimportant when SEM/DEM is
logic Level “0”.
Selecting RSET
Because the AD9561 must provide full range coverage of the
CLOCK pulse period, the ramp time must be matched to the
CLOCK period. All components for the ramp generators, except
RSET, are integrated in the AD9561.
RSET, is selected by the user to set the ramp time close to the
CLOCK period. The ramps are generated by constant current
sources charging on-chip capacitors.
RSET can be chosen in the range from 226 Ω for 60 MHz
operation to 16.5 kΩ for 1 MHz. Because the absolute value of
the on-chip capacitor can vary by ± 20%, the autocalibration
circuit is included to fine tune the matching of the ramp time to
the CLOCK period.
100
where F is the CLOCK frequency in Hz. The resistor value
determined by the equation will generate a current near center-
range of the autocalibration circuit.
Autocalibration
The AD9561 should be calibrated when power is applied to the
system or after a power reduce cycle.
CAL START
1µs MIN
CAL OUT
tAC
Figure 4. Autocalibration Timing
Autocalibration is initiated by applying a pulse of 1 µs minimum
duration to Pin 17, CAL START. The CLOCK pulse should be
applied continuously during calibration. As Figure 4 shows, the
initial state of CAL OUT is not known.
During the CAL IN pulse, all internal logic is initialized for
calibration and proper synchronization once calibration is
complete; the falling edge of CAL IN initiates the Auto-CAL
cycle.
Auto-CAL is not affected by the code applied to the DATA or
CONTROL inputs. However, to assure that no pulses are
generated during calibration, it is suggested that all digital
inputs be held at Logic “0.”
On the falling edge of CAL IN, the ramp’s slope is set as slow as
possible for the current RSET. Figure 4 shows the RAMP slope
increasing as autocalibration adds small incremental currents,
until it crosses the internal REF LO before the end of the
CLOCK period.
RAMP
END OF CLOCK CYCLE
10
1
0 1 10 20
RSET – kΩ
Figure 3. RSET Values vs. CLOCK Frequency
Figure 3 shows approximate values for RSET over the operating
frequency range. The following equation should be used to
determine RSET:
R
=
30.2068 ×109
F1.04414
REF LO
TIME
RAMP
Figure 5. Autocalibration Conceptual
The calibration current is incremented on each 32nd CLOCK
pulse until the full-scale ramp time is equal to the period of the
CLOCK. Cal Complete is detected and CAL OUT goes high
when the ramp crosses REF LO before it is reset by the next
CLOCK. With a maximum of 64 incremental increases, the
maximum autocalibration time, tAC, can be calculated by the
equation:
t AC
=
32 × 64
FC
where:
FC = CLOCK frequency in Hertz
REV. 0
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD9561.PDF ] | |
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