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AD9280 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9280
Beschreibung CMOS A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD9280 Datasheet, Funktion
a
Complete 8-Bit, 32 MSPS, 95 mW
CMOS A/D Converter
AD9280
FEATURES
CMOS 8-Bit 32 MSPS Sampling A/D Converter
Pin-Compatible with AD876-8
Power Dissipation: 95 mW (3 V Supply)
Operation Between +2.7 V and +5.5 V Supply
Differential Nonlinearity: 0.2 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
PRODUCT DESCRIPTION
The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9280 uses a multistage
differential pipeline architecture at 32 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the AD9280 has been designed to ease the devel-
opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
The sample-and-hold amplifier (SHA) is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and beyond the Nyquist rate. AC-coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit. The dynamic performance is excellent.
The AD9280 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9280 can operate with a supply range from +2.7 V to
+5.5 V, ideally suiting it for low power operation in high speed
applications.
The AD9280 is specified over the industrial (–40°C to +85°C)
temperature range.
PRODUCT HIGHLIGHTS
Low Power
The AD9280 consumes 95 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.
Very Small Package
The AD9280 is available in a 28-lead SSOP package.
Pin Compatible with AD876-8
The AD9280 is pin compatible with the AD876-8, allowing
older designs to migrate to lower supply voltages.
300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either single-
ended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9280’s input range.
Built-In Clamp Function
Allows dc restoration of video signals.
FUNCTIONAL BLOCK DIAGRAM
CLAMP
CLAMP IN
CLK
AVDD
DRVDD
VINA
REFTF
REFTS
REFBS
REFBF
VREF
REFSENSE
SHA SHA GAIN
SHA GAIN SHA
GAIN
SHA
GAIN
A/D
A/D D/A
A/D D/A
A/D D/A
A/D D/A
CORRECTION LOGIC
1V AD9280
OUTPUT BUFFERS
AVSS
DRVSS
STBY
MODE
THREE-
STATE
OTR
D7 (MSB)
D0 (LSB)
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2010






AD9280 Datasheet, Funktion
SSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN CONFIGURATION
28-Lead Wide Body (SSOP)
AVSS 1
28 AVDD
DRVDD 2
27 AIN
DNC 3
26 VREF
DNC 4
25 REFBS
D0 5 AD9280 24 REFBF
D1 6 TOP VIEW 23 MODE
D2 7 (Not to Scale) 22 REFTF
D3 8
21 REFTS
D4 9
20 CLAMPIN
D5 10
19 CLAMP
D6 11
18 REFSENSE
D7 12
17 STBY
OTR 13
16 THREE-STATE
DRVSS 14
15 CLK
'NC = DO NOT CONNECT
AD9280
PIN FUNCTION DESCRIPTIONS
Name
AVSS
DRVDD
DNC
DNC
D0
D1
D2
D3
D4
D5
D6
D7
OTR
DRVSS
CLK
THREE-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
REFTF
MODE
REFBF
REFBS
VREF
AIN
AVDD
Description
Analog Ground
Digital Driver Supply
Do Not Connect
Do Not Connect
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7, Most Significant Bit
Out-of-Range Indicator
Digital Ground
Clock Input
HI: High Impedance State. LO: Normal Operation
HI: Power-Down Mode. LO: Normal Operation
Reference Select
HI: Enable Clamp Mode. LO: No Clamp
Clamp Reference Input
Top Reference
Top Reference Decoupling
Mode Select
Bottom Reference Decoupling
Bottom Reference
Internal Reference Output
Analog Input
Analog Supply
REV. E
–5–

6 Page









AD9280 pdf, datenblatt
AD9280
The actual reference voltages used by the internal circuitry of
the AD9280 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
10F 0.1F
0.1F 0.1F
REFTF
AD9280
REFBF
Figure 17. Reference Decoupling Network
Note: REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
REFBS = reference bottom, sense
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
2V
0V
1.0F 0.1F
AIN
REFTS
REFBS
VREF
REF
SENSE
SHA
AD9280 MODE
AVDD
10k
REFTF 0.1F
10k
10k
A2
A/D
CORE
4.2k0.1F
TOTAL
10F
10k
A1
1V
0.1F
REFBF
INTERNAL REFERENCE OPERATION
Figures 18, 19 and 20 show sample connections of the AD9280
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9280
for 1 V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0 µF tantalum capacitor in
parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor.
1V AIN
0V
REFTS
REFBS
1.0F 0.1F
VREF
REF
SENSE
SHA
AD9280
MODE
AVDD
10k
10k
10k
A2
REFTF 0.1F
A/D
CORE
4.2k0.1F
TOTAL
10F
10k
A1
1V
REFBF
0.1F
Figure 18. Internal Reference—1 V p-p Input Span
(Top/Bottom Mode)
Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
2V AIN
1V
+1.5V
REFTS
REFBS
1.0F 0.1F
VREF
REF
SENSE
SHA
AD9280
MODE
AVDD/2
10k
10k
A2
A/D
CORE
REFTF 0.1F
4.2k0.1F
TOTAL
10F
10k10k
A1
1V
REFBF
0.1F
Figure 20. Internal Reference 1 V p-p Input Span
(Center Span Mode)
REV. E
–11–

12 Page





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