PDF AD9241 Data sheet ( Hoja de datos )

Número de pieza	AD9241
Descripción	Complete 14-Bit/ 1.25 MSPS Monolithic A/D Converter
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de AD9241 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas
No Preview Available ! a FEATURES Monolithic 14-Bit, 1.25 MSPS A/D Converter Low Power Dissipation: 60 mW Single +5 V Supply Integral Nonlinearity Error: 2.5 LSB Differential Nonlinearity Error: 0.6 LSB Input Referred Noise: 0.36 LSB Complete: On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 78.0 dB Spurious-Free Dynamic Range: 88.0 dB Out-of-Range Indicator Straight Binary Output Data 44-Pin MQFP Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter AD9241 FUNCTIONAL BLOCK DIAGRAM VINA VINB CML CAPT CAPB VREF SENSE SHA CLK AVDD DVDD DRVDD MDAC1 GAIN = 16 5 A/D 5 MDAC2 GAIN = 8 MDAC3 GAIN = 8 4 A/D 4 A/D 44 DIGITAL CORRECTION LOGIC 14 OUTPUT BUFFERS A/D 4 MODE SELECT 1V AD9241 REFCOM AVSS DVSS DRVSS OTR BIT 1 (MSB) BIT 14 (LSB) PRODUCT DESCRIPTION The AD9241 is a 1.25 MSPS, single supply, 14-bit analog-to- digital converter (ADC). It combines a low cost, high speed CMOS process and a novel architecture to achieve the resolution and speed of existing hybrid implementations at a fraction of the power consumption and cost. It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. An external refer- ence can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a multistage differential pipelined architecture with digital output error correc- tion logic to guarantee no missing codes over the full operating temperature range. The input of the AD9241 is highly flexible, allowing for easy interfacing to imaging, communications, medical, and data- acquisition systems. A truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. The sample-and-hold amplifier (SHA) is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. Also, the AD9241 performs well in communication systems employ- ing Direct-IF Down Conversion since the SHA in the differen- tial input mode can achieve excellent dynamic performance well beyond its specified Nyquist frequency of 0.625 MHz. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an over- flow condition which can be used with the most significant bit to determine low or high overflow. PRODUCT HIGHLIGHTS The AD9241 offers a complete single-chip sampling 14-bit, analog-to-digital conversion function in a 44-pin Metric Quad Flatpack. Low Power and Single Supply The AD9241 consumes only 60 mW on a single +5 V power supply. Excellent DC Performance Over Temperature The AD9241 provides no missing codes, and excellent tempera- ture drift performance over the full operating temperature range. Excellent AC Performance and Low Noise The AD9241 provides nearly 13 ENOB performance and has an input referred noise of 0.36 LSB rms. Flexible Analog Input Range The versatile onboard sample-and-hold (SHA) can be configured for either single-ended or differential inputs of varying input spans. Flexible Digital Outputs The digital outputs can be configured to interface with +3 V and +5 V CMOS logic families. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 1 page AD9241 PIN FUNCTION DESCRIPTIONS Pin Number Name Description 1 2, 29 3 4, 28 5 6 7 8–10 11 12–23 24 25 26, 27, 30 31 32 33 34, 35, 38 40, 43, 44 36 37 39 41 42 DVSS AVSS DVDD AVDD DRVSS DRVDD CLK NC BIT 14 BIT 13–BIT 2 BIT 1 OTR NC SENSE VREF REFCOM NC Digital Ground Analog Ground +5 V Digital Supply +5 V Analog Supply Digital Output Driver Ground Digital Output Driver Supply Clock Input Pin No Connect Least Significant Data Bit (LSB) Data Output Bits Most Significant Data Bit (MSB) Out of Range No Connect Reference Select Reference I/O Reference Common No Connect CAPB CAPT CML VINA VINB Noise Reduction Pin Noise Reduction Pin Common-Mode Level (Midsupply) Analog Input Pin (+) Analog Input Pin (–) DEFINITIONS OF SPECIFICATION INTEGRAL NONLINEARITY (INL) INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. ZERO ERROR The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions, and the ideal differ- ence between first and last code transitions. OVERVOLTAGE RECOVERY TIME Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter’s range. TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the maximum change from the initial (+25°C) value to the value at TMIN or TMAX. POWER SUPPLY REJECTION The specification shows the maximum change in full scale, from the value with the supply at the minimum limit to the value with the supply at its maximum limit. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. APERTURE DELAY Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO S/N+D is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the num- ber of bits. Using the following formula, N = (SINAD – 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal; this is expressed as a percentage or in decibels. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. SPURIOUS FREE DYNAMIC RANGE (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. TWO-TONE SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). REV. 0 –5– 5 Page AD9241 REFERENCE OPERATION The AD9241 contains an onboard bandgap reference that pro- vides a pin-strappable option to generate either a 1 V or 2.5 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2.5 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin-strapping options for the AD9241 reference configurations. Figure 26 shows a simplified model of the internal voltage refer- ence of the AD9241. A pin-strappable reference amplifier buff- ers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the A/D. This input span equals, Full-Scale Input Span = 2 × VREF TO A/D 5kΩ AD9241 5kΩ A2 5kΩ DISABLE A2 5kΩ LOGIC A1 1V DISABLE A1 LOGIC CAPT CAPB VREF 7.5kΩ SENSE 5kΩ REFCOM Figure 26. Equivalent Reference Circuit The voltage appearing at the VREF pin, and the state of the internal reference amplifier, A1, are determined by the voltage appearing at the SENSE pin. The logic circuitry contains two comparators that monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of A1. If the SENSE pin is tied to REFCOM, the switch is connected to the internal resistor network thus providing a VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch is connected to the SENSE pin. A short will provide a VREF of 1.0 V while an external resistor network will provide an alternative VREF between 1.0 V and 2.5 V. The second comparator controls internal circuitry that will disable the reference amplifier if the SENSE pin is tied to AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference. The actual reference voltages used by the internal circuitry of the AD9241 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple these pins. Figure 27 shows the recommended decoupling network. This capacitive network performs the following three functions: (1) in conjunction with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the A/D internal circuitry, (2) it provides the necessary compensation for A2, and (3) it bandlimits the noise contribution from the refer- ence. The turn-on time of the reference voltage appearing be- tween CAPT and CAPB is approximately 15 ms and should be evaluated in any power-down mode of operation. CAPT AD9241 0.1µF 0.1µF 10µF CAPB 0.1µF Figure 27. Recommended CAPT/CAPB Decoupling Network The A/D’s input span may be varied dynamically by changing the differential reference voltage appearing across CAPT and CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low noise amplifiers. In this case, both internal amplifiers (i.e., A1 and A2) must be disabled by connecting SENSE to AVDD and VREF to REFCOM, and the capacitive decoupling network removed. The external voltages applied to CAPT and CAPB must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec- tively where the input span can be varied between 2 V and 5 V. Note that those samples within the pipeline A/D during any reference transition will be corrupted and should be discarded. Reference Operating Mode INTERNAL INTERNAL INTERNAL EXTERNAL (NONDYNAMIC) EXTERNAL (DYNAMIC) Table II. Reference Configuration Summary Input Span (VINA–VINB) (V p-p) Required VREF (V) Connect 2 5 2 ≤ SPAN ≤ 5 AND SPAN = 2 × VREF 2 ≤ SPAN ≤ 5 2 ≤ SPAN ≤ 5 1 2.5 1 ≤ VREF ≤ 2.5 AND VREF = (1 + R1/R2) 1 ≤ VREF ≤ 2.5 CAPT and CAPB Externally Driven SENSE SENSE R1 R2 SENSE VREF SENSE VREF EXT. REF. 1 EXT. REF. 2 To VREF REFCOM VREF AND SENSE SENSE AND REFCOM AVDD EXT. REF. AVDD REFCOM CAPT CAPB REV. 0 –11– 11 Page

Páginas	Total 24 Páginas
PDF Descargar	[ Datasheet AD9241.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AD9240	Monolithic A/D Converter	Analog Devices
AD9241	Complete 14-Bit/ 1.25 MSPS Monolithic A/D Converter	Analog Devices
AD9243	Monolithic A/D Converter	Analog Devices
AD9244	14-Bit 40/65 MSPS Monolithic A/D Converter	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar