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AD9229 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9229
Beschreibung Quad 12-Bit 50/65 MSPS Serial LVDS 3V A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9229 Datasheet, Funktion
FEATURES
Four ADCs in 1 package
Serial LVDS digital output data rates
to 780 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 69.5 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
400 MHz full power analog bandwidth
Power dissipation
1,350 mW at 65 MSPS
985 mW at 50 MSPS
1 V p-p to 2 V p-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
APPLICATIONS
Digital beam-forming systems for ultrasound
Wireless and wired broadband communications
Communication test equipment
GENERAL DESCRIPTION
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance in applications
where a small package size is critical.
The ADC requires a single 3 V power supply and TTL-/CMOS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported and typically consumes 3 mW when enabled.
Fabricated with an advanced CMOS process, the AD9229 is
available in a Pb-free, 48-lead LFCSP package. It is specified
over the industrial temperature range of –40°C to +85°C.
Quad, 12-Bit, 50/65 MSPS,
Serial, LVDS, 3 V A/D Converter
AD9229
VIN+A
VIN–A
VIN+B
VIN–B
VIN+C
VIN–C
VIN+D
VIN–D
FUNCTIONAL BLOCK DIAGRAM
PDWN DTP
DRVDD DRGND
AD9229
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+A
D–A
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+B
D–B
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+C
D–C
SHA
PIPELINE 12 SERIAL
ADC
LVDS
D+D
D–D
VREF
SENSE
REFT
REFB
REF
SELECT
0.5V
DATA RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
AGND LVDSBIAS
Figure 1.
CLK
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. A data clock out (DCO) is provided, which operates up to
390 MHz and supports double-data rate operation (DDR).
3. The outputs of each ADC are serialized LVDS with data
rates up to 780 Mbps (12 bits × 65 MSPS).
4. The AD9229 operates from a single 3.0 V power supply.
5. Packaged in a Pb-free, 48-lead LFCSP package.
6. The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved.






AD9229 Datasheet, Funktion
AD9229
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
CLOCK INPUT
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC INPUTS (PDWN)
Logic 1 Voltage
Logic 0 Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUTS (D+, D–)
Logic Compliance
Differential Output Voltage
Output Offset Voltage
Output Coding
Temperature
Full
Full
Full
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Test
Level
Min
AD9229-50
Typ Max Min
AD9229-65
Typ Max Unit
TTL/CMOS
TTL/CMOS
IV 2.0
2.0 V
IV 0.8 0.8 V
VI
0.5 ±10
0.5 ±10 μA
VI
0.5 ±10
0.5 ±10 μA
V2
2 pF
IV 2.0
IV
IV
IV
V
2.0
0.8
0.5 ±10
0.5 ±10
2
V
0.8 V
0.5 ±10 μA
0.5 ±10 μA
2 pF
LVDS
LVDS
VI 260
440 260
440 mV
VI 1.15
1.25 1.35 1.15
1.25 1.35 V
VI Offset
binary
Offset
binary
Rev. B | Page 5 of 40

6 Page









AD9229 pdf, datenblatt
TYPICAL PERFORMANCE CHARACTERISTICS
0
AIN = –0.5dBFS
SNR = 70.4dB
–20 ENOB = 11.4 BITS
SFDR = 85.8dBC
–40
–60
–80
–100
–120
0
4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5
FREQUENCY (MHz)
Figure 9. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 65 MSPS
0
AIN = –0.5dBFS
SNR = 69.6dB
–20 ENOB = 11.3 BITS
SFDR = 82.4dBC
–40
–60
–80
–100
–120
0
4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5
FREQUENCY (MHz)
Figure 10. Single-Tone 32k FFT with fIN = 30 MHz, fSAMPLE = 65 MSPS
AD9229
0
AIN = –0.5dBFS
SNR = 68.1dB
–20 ENOB = 11.0 BITS
SFDR = 77.0dBC
–40
–60
–80
–100
–120
0
4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5
FREQUENCY (MHz)
Figure 12. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
90
1V p-p, SFDR (dBc)
85
2V p-p, SFDR (dBc)
80
75
2V p-p, SNR (dB)
70
65 1V p-p, SNR (dB)
AIN = –0.5dBFS
60
10 15 20 25 30 35 40 45 50
ENCODE (MSPS)
Figure 13. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 50 MSPS
0
AIN = –0.5dBFS
SNR = 68.5dB
–20 ENOB = 11.1 BITS
SFDR = 81.3dBC
–40
–60
–80
–100
–120
0
4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5
FREQUENCY (MHz)
Figure 11. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
90
1V p-p, SFDR (dBc)
85
80 2V p-p, SFDR (dBc)
75
2V p-p, SNR (dB)
70
65 1V p-p, SNR (dB)
AIN = –0.5dBFS
60
10 15 20 25 30 35 40 45 50
ENCODE (MSPS)
Figure 14. SNR/SFDR vs. fSAMPLE, fIN = 25 MHz, fSAMPLE = 50 MSPS
Rev. B | Page 11 of 40

12 Page





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