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PDF AD9225 Data sheet ( Hoja de datos )
| Número de pieza | AD9225 | |
| Descripción | Complete 12-Bit 25 MSPS Monolithic A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Monolithic 12-Bit, 25 MSPS ADC
Low Power Dissipation: 280 mW
Single 5 V Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: ؎0.4 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 71 dB
Spurious-Free Dynamic Range: –85 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC
28-Lead SSOP
Compatible with 3 V Logic
Complete 12-Bit, 25 MSPS
Monolithic A/D Converter
AD9225
FUNCTIONAL BLOCK DIAGRAM
VINA
VINB
CAPT
CAPB
VREF
SENSE
SHA
CLK
AVDD
DRVDD
MDAC1
GAIN = 16
5
ADC
5
MDAC2
GAIN = 4
MDAC3
GAIN = 4
3
ADC
ADC 3
33
DIGITAL CORRECTION LOGIC
12
OUTPUT BUFFERS
ADC
4
MODE
SELECT
1V
REFCOM
AVSS
AD9225
DRVSS CML
OTR
BIT 1
(MSB)
BIT 12
(LSB)
GENERAL DESCRIPTION
The AD9225 is a monolithic, single-supply, 12-bit, 25 MSPS
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier and voltage reference. The AD9225
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 25 MSPS
data rates, and guarantees no missing codes over the full operat-
ing temperature range.
The AD9225 combines a low cost, high speed CMOS process
and a novel architecture to achieve the resolution and speed of
existing bipolar implementations at a fraction of the power
consumption and cost.
The input of the AD9225 allows for easy interfacing to both
imaging and communications systems. With the device’s truly
differential input structure, the user can select a variety of input
ranges and offsets, including single-ended applications. The
dynamic performance is excellent.
The sample-and-hold amplifier (SHA) is well suited for both
multiplexed systems that switch full-scale voltage levels in succes-
sive channels and sampling single-channel inputs at frequencies
up to and well beyond the Nyquist rate.
The AD9225’s wideband input, combined with the power and
cost savings over previously available monolithics, suits applica-
tions in communications, imaging, and medical ultrasound.
The AD9225 has an on-board programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of an application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal indicates an overflow
condition that can be used with the most significant bit to deter-
mine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9225 is fabricated on a very cost effective CMOS pro-
cess. High speed precision analog circuits are combined with
high density logic circuits.
The AD9225 offers a complete, single-chip sampling, 12-bit,
25 MSPS analog-to-digital conversion function in 28-lead
SOIC and SSOP packages.
Low Power—The AD9225 at 280 mW consumes a fraction of
the power presently available in monolithic solutions.
On-Board Sample-and-Hold Amplifier (SHA)—The versa-
tile SHA input can be configured for either single-ended or
differential inputs.
Out-of-Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9225’s input range.
Single Supply—The AD9225 uses a single 5 V power supply,
simplifying system power supply design. It also features a sepa-
rate digital driven supply line to accommodate 3 V and 5 V logic
families.
Pin Compatibility—The AD9225 is pin compatible with the
AD9220, AD9221, AD9223, and AD9224 ADCs.
Rev. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax:781/461-3113 ©1998-2011Analog Devices, Inc. All rights reserved.
1 page  
AD9225
ABSOLUTE MAXIMUM RATINGS*
Pin Name
With
Respect to
Min
Max
Unit
AVDD
AVSS
–0.3 +6.5
V
DRVDD
DRVSS
–0.3 +6.5
V
AVSS
DRVSS
–0.3 +0.3
V
AVDD
DRVDD –6.5 +6.5
V
REFCOM
AVSS
–0.3 +0.3
V
CLK
AVSS
–0.3
AVDD + 0.3
V
Digital Outputs
DRVSS
–0.3
DRVDD + 0.3
V
VINA, VINB
AVSS
–0.3
AVDD + 0.3
V
VREF
AVSS
–0.3
AVDD + 0.3
V
SENSE
AVSS
–0.3
AVDD + 0.3
V
CAPB, CAPT
AVSS
–0.3
AVDD + 0.3
V
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
150
–65 +150
300
∞C
∞C
∞C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
ANALOG
INPUT
INPUT
CLOCK
DATA
OUTPUT
S1 S2
tC
tCH tCL
S4
S3
Figure 1. Timing Diagram
tOD
DATA 1
PIN CONFIGURATION
28-Lead SOIC and SSOP
CLK 1
28 DRVDD
(LSB) BIT 12 2
27 DRVSS
BIT 11 3
26 AVDD
BIT 10 4
25 AVSS
BIT 9 5
24 VINB
BIT 8 6 AD9225 23 VINA
BIT 7 7 TOP VIEW 22 CML
BIT 6 8 (Not to Scale) 21 CAPT
BIT 5 9
20 CAPB
BIT 4 10
19 REFCOM
BIT 3 11
18 VREF
BIT 2 12
17 SENSE
(MSB) BIT 1 13
16 AVSS
OTR 14
15 AVDD
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
Rev. C
5 Page 
AD9225
REFERENCE OPERATION
The AD9225 contains an on-board band gap reference that
provides a pin strappable option to generate either a 1 V or 2 V
output. With the addition of two external resistors, the user can
generate reference voltages other than 1 V and 2 V. Another
alternative is to use an external reference for designs requiring
enhanced accuracy and/or drift performance. See Table II for
a summary of the pin strapping options for the AD9225 refer-
ence configurations.
Figure 5 shows a simplified model of the internal voltage
reference of the AD9225. A pin strappable reference amplifier
buffers a 1 V fixed reference. The output from the reference
amplifier, A1, appears on the VREF pin. The voltage on the
VREF pin determines the full-scale input span of the ADC.
This input span equals
Full-Scale Input Span = 2 ¥ VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators that monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to AVSS (AGND), the switch is
connected to the internal resistor network thus providing a
VREF of 2.0 V. If the SENSE pin is tied to the VREF pin via
a short or resistor, the switch will connect to the SENSE pin.
This short will provide a VREF of 1.0 V. An external resistor
network will provide an alternative VREF between 1.0 V and
2.0 V. The other comparator controls internal circuitry that will
disable the reference amplifier if the SENSE pin is tied AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
TO
A/D
5k⍀
AD9225
5k⍀
A2
5k⍀
DISABLE
A2
5k⍀
LOGIC
CAPT
CAPB
A1
1V
VREF
6.25k⍀
DISABLE
A1
LOGIC
6.25k⍀
SENSE
REFCOM
Figure 5. Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9225 appears on the CAPT and CAPB pins. For proper
operation when using the internal or an external reference, it is
necessary to add a capacitor network to decouple these pins.
Figure 6 shows the recommended decoupling network. This
capacitive network performs the following three functions: (1)
along with the reference amplifier, A2, it provides a low source
impedance over a large frequency range to drive the ADC inter-
nal circuitry, (2) it provides the necessary compensation for A2,
and (3) it bandlimits the noise contribution from the reference.
The turn-on time of the reference voltage appearing between
CAPT and CAPB is approximately 15 ms and should be evalu-
ated in any power-down mode of operation.
CAPT
AD9225
CAPB
0.1F
0.1F
10F
0.1F
Figure 6. Recommended CAPT/CAPB
Decoupling Network
The ADC’s input span may be varied dynamically by changing the
differential reference voltage appearing across CAPT and CAPB
symmetrically around 2.5 V (i.e., midsupply). To change the refer-
ence at speeds beyond the capabilities of A2, it will be necessary to
drive CAPT and CAPB with two high speed, low noise amplifiers.
In this case, both internal amplifiers (i.e., A1 and A2) must be
disabled by connecting SENSE to AVDD, connecting VREF to
AVSS and removing the capacitive decoupling network. The exter-
nal voltages applied to CAPT and CAPB must be 2.0 V + Input
Span/4 and 2.0 V – Input Span/4, respectively, in which the input
span can be varied between 2 V and 4 V. Note that those samples
within the pipeline ADC during any reference transition will be
corrupted and should be discarded.
DRIVING THE ANALOG INPUTS
The AD9225 has a highly flexible input structure allowing it to
interface with single ended or differential input interface cir-
cuitry. The applications shown in this section and the Reference
Configurations section along with the information presented in
the Input and Reference Overview give examples of single-
ended and differential operation. Refer to Tables I and II for a
list of the different possible input and reference configurations
and their associated figures in the data sheet.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power supply
options. For example, a dc-coupled single-ended input would
be appropriate for most data acquisition and imaging applica-
tions. Many communication applications, which require a
dc-coupled input for proper demodulation, can take advantage
of the excellent single-ended distortion performance of the
AD9225. The input span should be configured so the system’s
performance objectives and the headroom requirements of the
driving op amp are simultaneously met.
–10–
Rev. C
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AD9225.PDF ] | |
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