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PDF AD9224 Data sheet ( Hoja de datos )
| Número de pieza | AD9224 | |
| Descripción | Complete 12-Bit 40 MSPS Monolithic A/D Converter | |
| Fabricantes | Analog Devices | |
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FEATURES
Monolithic 12-Bit, 40 MSPS A/D Converter
Low Power Dissipation: 415 mW
Single +5 V Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: ؎0.33 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 68.3 dB
Spurious-Free Dynamic Range: 81 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SSOP Package
Compatible with 3 V Logic
Complete 12-Bit, 40 MSPS
Monolithic A/D Converter
AD9224
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DRVDD
VINA
VINB
SHA
MDAC1
GAIN = 16
MDAC2
GAIN = 4
MDAC3
GAIN = 4
CML
5
A/D
3
A/D
3
A/D
A/D
CAPT 5 3 3 4
CAPB
DIGITAL CORRECTION LOGIC
VREF
12
OUTPUT BUFFERS
OTR
SENSE
MODE
SELECT
1V
AD9224
BIT 1
(MSB)
BIT 12
(LSB)
REFCOM
AVSS DRVSS
PRODUCT DESCRIPTION
The AD9224 is a monolithic, single supply, 12-bit, 40 MSPS,
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier and voltage reference. The AD9224
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 40 MSPS
data rates, and guarantees no missing codes over the full operat-
ing temperature range.
The AD9224 combines a low cost high speed CMOS process
and a novel architecture to achieve the resolution and speed of
existing bipolar implementations at a fraction of the power
consumption and cost.
The input of the AD9224 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets, including single-ended applications. The dynamic per-
formance is excellent.
The sample-and-hold (SHA) amplifier is well suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and well beyond the Nyquist rate.
The AD9224’s wideband input, combined with the power and
cost savings over previously available monolithics, is suitable for
applications in communications, imaging and medical ultrasound.
The AD9224 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal indicates an overflow
condition which can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9224 is fabricated on a very cost effective CMOS
process. High speed precision analog circuits are now combined
with high density logic circuits.
The AD9224 offers a complete single-chip sampling 12-bit,
40 MSPS analog-to-digital conversion function in 28-lead
SSOP package.
Low Power—The AD9224 at 415 mW consumes a fraction of
the power of presently available in existing monolithic solutions.
On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or differential
inputs.
Out of Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9224’s input range.
Single Supply—The AD9224 uses a single +5 V power supply
simplifying system power supply design. It also features a sepa-
rate digital driver supply line to accommodate 3 V and 5 V logic
families.
Pin Compatibility—The AD9224 is pin compatible with the
AD9220, AD9221, AD9223 and AD9225 ADCs.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD9224
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TMIN or TMAX.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
REV. A
–5–
5 Page 
AD9224
Table I. Analog Input Configuration Summary
Input
Connection
Single-Ended
Input
Coupling Span (V)
DC 2
2 × VREF
␣ ␣ ␣ ␣ ␣ ␣ Input Range (V)
VINA1
VINB1
0 to 2
1
0 to
2 × VREF
VREF
Figure
#
19, 20
Comments
Best for stepped input response applications, requires ± 5 V op amp.
19, 20
Same as above but with improved noise performance due to
increase in dynamic range. Headroom/settling time require-
ments of ± 5 op amp should be evaluated.
4
0 to 4
2.0
19, 20
Optimum noise performance, excellent SNR performance, often
requires low distortion op amp with VCC > +5 V due to its head-
room issues.
2 × VREF
2.0 – VREF
␣ ␣ ␣ ␣ to
2.0 + VREF
2.0
30 Optimum THD performance with VREF = 1. Single supply
operation (i.e., +5 V) for many op amps.
Single-Ended AC
2 or
0 to 1 or
1 or VREF
2 × VREF 0 to 2 × VREF
21, 22
4
0.5 to 4.5
2.5
2 × VREF
2.0 – VREF
␣ ␣ ␣ ␣ to
2.0 + VREF
2.0
22 Optimum noise performance, excellent THD performance,
ability to use ± 5 V op amp.
21 Flexible input range, Optimum THD performance with
VREF = 1. Ability to use either +5 V or ± 5 V op amp.
Differential
AC/DC
(via Transformer)
or Amplifier
2
2 to 3
3 to 2
23, 24
Optimum full-scale THD and SFDR performance well beyond
the A/Ds Nyquist frequency. Preferred mode for undersampling
applications.
2 × VREF
2.0 – VREF/2 2.0 + VREF/2 23, 24
␣ ␣ ␣ ␣ to ␣ ␣ ␣ ␣ to
2.0 + VREF/2 2.0 – VREF/2
Same as above with the exception that full-scale THD and SFDR
performance can be traded off for better noise performance.
4.0
1.5 to 3.5
3.5 to 1.5
23, 24 Optimum noise performance.
NOTE
1VINA and VINB can be interchanged if signal inversion is required.
Reference
Operating Mode
INTERNAL
INTERNAL
INTERNAL
EXTERNAL
(NONDYNAMIC)
EXTERNAL
(DYNAMIC)
Table II. Reference Configuration Summary
Input Span (VINA–VINB)
(V p-p)
2
4
2 ≤ SPAN ≤ 4 AND
SPAN = 2 × VREF
2 ≤ SPAN ≤ 4
2 ≤ SPAN ≤ 4
Required VREF (V)
1
2
1 ≤ VREF ≤ 2.0 AND
VREF = (1 + R1/R2)
1 ≤ VREF ≤ 2.0
CAPT and CAPB
Externally Driven
Connect
SENSE
SENSE
R1
R2
SENSE
VREF
SENSE
VREF
EXT. REF.
EXT. REF.
To
VREF
REFCOM
VREF AND SENSE
SENSE AND REFCOM
AVDD
EXT. REF.
AVDD
AVSS
CAPT
CAPB
REV. A
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9224.PDF ] | |
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