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PDF AD9100 Data sheet ( Hoja de datos )
| Número de pieza | AD9100 | |
| Descripción | Ultrahigh Speed Monolithic Track-and-Hold | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Ultrahigh Speed
Monolithic Track-and-Hold
AD9100*
FEATURES
Excellent Hold Mode Distortion into 250 ⍀
–88 dB @ 30 MSPS (2.3 MHz VIN)
–83 dB @ 30 MSPS (12.1 MHz VIN)
–74 dB @ 30 MSPS (19.7 MHz VIN)
16 ns Acquisition Time to 0.01%
<1 ps Aperture Jitter
250 MHz Tracking Bandwidth
83 dB Feedthrough Rejection @ 20 MHz
3.3 nV/√Hz Spectral Noise Density
MlL-STD-Compliant Versions Available
APPLICATIONS
A/D Conversion
Direct IF Sampling
Imaging/FLIR Systems
Peak Detectors
Radar/EW/ECM
Spectrum Analysis
CCD ATE
GENERAL DESCRIPTION
The AD9100 is a monolithic track-and-hold amplifier which
sets a new standard for high speed and high dynamic range
applications. It is fabricated in a mature high speed complemen-
tary bipolar process. In addition to innovative design topologies,
a custom package is utilized to minimize parasitics and optimize
dynamic performance.
Acquisition time (hold to track) is 13 ns to 0.1% accuracy, and
16 ns to 0.01%. The AD9100 boasts superlative hold-mode
frequency domain performance; when sampling at 30 MSPS
hold mode distortion is less than 83 dBfs for analog frequencies
up to 12 MHz; and –74 dBfs at 20 MHz. The AD9100 can also
drive capacitive loads up to 100 pF with little degradation in
acquisition time; it is therefore well suited to drive 8- and 10-bit
flash converters at clock speeds to 50 MSPS. With a spectral
noise density of 3.3 nV/√Hz and feedthrough rejection of 83 dB
at 20 MHz, the AD9100 is well suited to enhance the dynamic
range of many 8- to 16-bit systems.
FUNCTIONAL BLOCK DIAGRAM
CLK CLK
50⍀
VIN
A1 SWITCH CHOLD
22pF
A2
؎2.3V
CLAMP
AD9100
VOUT
The AD9100 is “user friendly” and easy to apply: (1) it requires
+5 V/–5.2 V power supplies; (2) the hold capacitor and switch
power supply decoupling capacitors are built into the DIP pack-
age; (3) the encode clock is differential ECL to minimize clock
jitter; (4) the input resistance is typically 800 kΩ; (5) the analog
input is internally clamped to prevent damage from voltage
transients.
The AD9100 is available in a 20-lead side-brazed “skinny DIP”
package. Commercial, industrial, and military temperature
grade parts are available. Consult the factory for information
about the availability of 883-qualified devices.
PRODUCT HIGHLIGHTS
1. Hold Mode Distortion is guaranteed.
2. Monolithic construction.
3. Analog input is internally clamped to protect against over-
voltage transients and ensure fast recovery.
4. Output is short circuit protected.
5. Drives capacitive loads to 100 pF.
6. Differential ECL clock inputs.
*Patent pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
0
–5
–10
DC 60 120 180 240 300
INPUT FREQUENCY – MHz
Figure 2. Gain vs. Frequency (Track
Mode)
–95
VO = 2V p-p
ENCODE = 30 MSPS
–90
RL = 250⍀
–85
Typical Performance Characteristics–AD9100
60 50
AD9100
50
RS
40
CL 1k⍀
40 30
30
20
10
DC
60 120 180 240
INPUT FREQUENCY – MHz
300
Figure 3. Power Supply Rejection
Ratio vs. Frequency
50
40
20
10 NO RS NEEDED WHEN
CL IS LESS THAN 6pF
0
0 20 40 60 80 100
C LOAD – pF
Figure 4. Recommended RS vs. CLOAD
for Optimal Settling Times
TRACK
TRACK
HOLD
30
–80
RL = 100⍀
–75
–70
0
4 8 12 16
INPUT FREQUENCY – MHz
20
Figure 5. Worst Hold Mode Harmonic
vs. Analog Input Frequency
58
AD9060 + AD9100
C
53 HOLD = 22pF
AD9060
48
AIN = 3.5V p-p
ENCODE = 40 MSPS
43
DC
10 20 30
INPUT FREQUENCY – MHz
40
Figure 8. SNR vs. Analog Input
105
95
BEYOND
CAPABILITY
85 OF AVAILABLE
MEASUREMENT
TOOLS
75
65
20 WORST CASE
10 TYPICAL
0
–50
0 +25
+75 +125
TEMPERATURE – ؇C
Figure 6. Magnitude of Droop Rate
vs. Temperature
AD9100
AIN
27⍀
AD9060
10 FFT
PROC
CH*
THE AD9060 IS A 10-BIT, 75MSPS MONOLITHIC
ADC FROM ANALOG DEVICES.
* THE AD9100XD (DIP) HAS AN INTERNAL 22pF
HOLD CAPACITOR.
Figure 9.
1.0
VOUT = 2V STEP
10ns
10ns
100ns/DIV
Figure 7. Track-to-Hold-to-Track Switch
Transients
58
AD9060 + AD9100
56
54
AD9060
CHOLD = 10pF
C
HOLD = 22pF
52
AIN = 3.5V p-p
ENCODE = 20 MSPS
50
DC
5 10 15
INPUT FREQUENCY – MHz
20
Figure 10. SNR vs. Analog Input
0.1
0.01
55
12
10 20
100
INPUT FREQUENCY – MHz
Figure 11. Feedthrough Rejection vs.
Input Frequency
REV. B
0.001
10 12 14 16 18 20
ns
Figure 12. Settling Tolerance vs.
Acquisition Time
–5–
5 Page 
0
VOUT = 2V p-p
RLOAD = 100⍀
ENCODE = 30 MSPS
20 tTRACK = 20ns
tHOLD = 13.5ns
ALL HARMONICS
ARE ALIASED
40
60
80 5 9 4
100
6 832 7
120
Figure 25. Frequency (500 kHz/Division) Analog Input =
12.1 MHz
AD9100
0
VOUT = 2V p-p
RLOAD = 100⍀
ENCODE = 30 MSPS
20 tTRACK = 20ns
tHOLD = 13.5ns
ALL HARMONICS
ARE ALIASED
40
60
80
100
120
Figure 27. Frequency (500 kHz/Division) Analog Input =
19.8 MHz
2.5 (63.5)
4 PLACES
0.25 (6.35)
0.25 (6.35)
+VS
J7
GND
J6
–VS
J5
a
)A( 90843
3.4
(86.36)
Figure 26. Bottom of AD9100/PCB Evaluation Board Viewed
from Above
AD9100
EVALUATION
BOARD
J4 CLOCK IN
C13
C12
U2
DUT
J3 VBUFF
J2 VOUT
W1
W3 U1
W2
TP3
J1 VIN
TP1
Figure 28. Top of AD9100/PCB Evaluation Board Viewed
from Above
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD9100.PDF ] | |
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