PDF AD9059 Data sheet ( Hoja de datos )

Número de pieza	AD9059
Descripción	Dual 8-Bit 60 MSPS A/D Converter
Fabricantes	Analog Devices
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No Preview Available ! Dual 8-Bit, 60 MSPS A/D Converter AD9059 FEATURES Dual 8-Bit ADCs on a Single Chip Low Power: 400 mW Typical On-Chip 2.5 V Reference and Track-and-Hold 1 V p-p Analog Input Range Single 5 V Supply Operation 5 V or 3 V Logic Interface 120 MHz Analog Bandwidth Power-Down Mode: <12 mW APPLICATIONS Digital Communications (QAM Demodulators) RGB and YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation FUNCTIONAL BLOCK DIAGRAM AINA VREF AINB VD PWRDN VDD AD9059 T/H ADCA 8 D7A–D0A 2.5V T/H ADCB ENCODE 8 D7B–D0B GND PIN CONFIGURATION PRODUCT DESCRIPTION The AD9059 is a dual 8-bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. With a 60 MSPS encode rate capability and full-power analog bandwidth of 120 MHz typical, the component is ideal for applications requiring multiple ADCs with excellent dynamic performance. To minimize system cost and power dissipation, the AD9059 includes an internal 2.5 V reference and dual track-and-hold circuits. The ADC requires only a 5 V power supply and an encode clock. No external reference or driver components are required for many applications. The AD9059’s single encode input is TTL/CMOS compatible and simultaneously controls both internal ADC channels. The parallel 8-bit digital outputs can be operated from 5 V or 3 V supplies. A power-down function may be exercised to bring total consumption to <12 mW when ADC data is not required for lengthy periods of time. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced BiCMOS process, the AD9059 is available in a space-saving 28-lead shrink small outline package (28-lead SSOP) and is specified over the industrial temperature range (–40°C to +85°C). Customers desiring single-channel digitization may consider the AD9057, a single 8-bit, 60 MSPS monolithic based on the AD9059 ADC core. The AD9057 is available in a 20-lead shrink small outline package (20-lead SSOP) and is specified over the industrial temperature range. AINA 1 28 AINB VREF 2 27 GND PWRDN 3 26 ENCODE VD 4 25 VD GND 5 VDD 6 24 GND AD9059 TOP VIEW 23 VDD D7A (MSB) 7 (Not to Scale) 22 D7B (MSB) D6A 8 21 D6B D5A 9 20 D5B D4A 10 19 D4B D3A 11 18 D3B D2A 12 17 D2B D1A 13 16 D1B D0A (LSB) 14 15 D0B (LSB) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page AD9059 N N+3 N+5 AIN N + 1 ENCODE tA tEH tEL N+2 N+4 DIGITAL OUTPUTS tV N–3 N–2 N–1 N N+1 N+2 tPD MIN TYP MAX tA APERTURE DELAY tEH PULSEWIDTH HIGH 6.7ns 2.7ns 166ns tEL PULSEWIDTH LOW 6.7ns 166ns tV OUTPUT VALID TIME 4.0ns 6.6n tPD OUTPUT PROP DELAY 9.5ns 14.2ns Figure 1. Timing Diagram PIN CONFIGURATION AINA 1 28 AINB VREF 2 27 GND PWRDN 3 26 ENCODE VD 4 25 VD GND 5 VDD 6 24 GND AD9059 TOP VIEW 23 VDD D7A (MSB) 7 (Not to Scale) 22 D7B (MSB) D6A 8 21 D6B D5A 9 20 D5B D4A 10 19 D4B D3A 11 18 D3B D2A 12 17 D2B D1A 13 16 D1B D0A (LSB) 14 15 D0B (LSB) Pin No. 1, 28 2 3 4, 25 5, 24, 27 6, 23 7–14 22–15 26 PIN FUNCTION DESCRIPTIONS Mnemonic Function AINA, AINB Analog Inputs for ADC A and B. VREF PWRDN VD GND VDD D7A–D0A D7B–D0B ENCODE Internal Voltage Reference (2.5 V Typical); Bypass with 0.1 µF to Ground or Overdrive with External Voltage Reference. Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to High- Impedance State). Analog 5 V Power Supply. Ground. Digital Output Power Supply. Nominally 3 V to 5 V. Digital Outputs of ADC A. Digital Outputs of ADC B. Encode Clock for ADCs A and B (ADCs Sample Simultaneously on the Rising Edge of ENCODE). Table I. Digital Coding (VREF = 2.5 V) Analog Input (V) Voltage Level Digital Output 3.0 2.502 2.498 2.0 Positive Full Scale Midscale + 1/2 LSB Midscale – 1/2 LSB Negative Full Scale 1111 1111 1000 0000 0111 1111 0000 0000 –4– REV. A 5 Page AD9059 ANALOG IN–A BNC J5 E7 E8 R13 E9 R11 50⍀ 1k⍀ ANALOG IN–B BNC J4 E4 R12 50⍀ R10 E5 1k⍀ E6 U4 AD8041Q 1 2 NC 3 DIS 8 +VS 7 6 5V 4 –VS 5 NC C12 0.1µF R5 10⍀ E14 E15 E13 R7 1k⍀ R15 1k⍀ R8 10k⍀ R9 10k⍀ C17 10µF C10 0.1µF J1, REF C8 0.1µF R14 1k⍀ 5V E2 E3 E1 PWRDN R8 1k⍀ U3 AD8041Q 1 NC 2 3 DIS 8 +VS 7 6 5V 4 –VS NC 5 E12 E11 R4 10⍀ E10 C11 0.1µF J9, VDD C16 C9 10µF U1 0.1µF AD9059RS 1 2 AINA 3 VREF 5V 4 5 PWRDN VD 6 GND 7 VDD D7A 8 D7A D6A D6A D5A 9 D5A D4A 10 D4A 11 D3A D3A D2A D1A 12 13 D2A D1A D0A 14 D0A AINB 28 27 GND ENC 26 VD 25 24 5V GND VDD 23 22 D7B D7B D6B 21 D6B D5B 20 D5B D4B 19 D4B D3B 18 D3B D2B 17 D2B D1B 16 D1B D0B 15 D0B J11, VD C6 0.1µF C7 0.1µF C14 0.1µF 5V C3 C4 C5 C13 C15 0.1µF 0.1µF 0.1µF 0.1µF 10µF DECOUPLING CAPS J12, GND BNC J10 ENCODE R15 50⍀ U7 74AC00 1 3 2 U7 74AC00 46 5 U7 74AC00 12 11 13 Figure 7. AD9059 Dual Evaluation Board Schematic U5 74ACQ574 9 D0B 8 8D D1B 7 7D D2B 6 6D D3B 5D 5 D4B 4 4D D5B 3D D6B 3 2D D7B 2 1D 12 8Q DB0 13 7Q 14 DB1 6Q 15 DB2 5Q 16 DB3 4Q DB4 3Q 17 DB5 2Q 18 DB6 1Q 19 DB7 CK OE 11 1 U6 74ACQ574 9 D7A 8 8D D6A D5A 7 6 7D 6D D4A 5D D3A 5 4 4D D2A 3D D1A 3 2D D0A 2 1D 12 8Q 13 DA7 7Q 14 DA6 6Q 15 DA5 5Q 16 DA4 4Q DA3 3Q 17 DA2 2Q 18 DA1 1Q 19 DA0 CK OE 11 1 P2 C37DRPF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DB0 22 DB1 23 DB2 24 25 DB3 DB4 26 27 DB5 DB6 28 DB7 29 DA0 30 DA1 31 DA2 32 DA3 33 34 DA4 DA5 35 DA6 36 DA7 37 –10– REV. A 11 Page

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