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AD9054 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9054
Beschreibung 8-Bit/ 200 MSPS A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD9054 Datasheet, Funktion
a
8-Bit, 200 MSPS
A/D Converter
AD9054
FEATURES
200 MSPS Guaranteed Conversion Rate
135 MSPS Low Cost Version Available
350 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal +2.5 V Reference and T/H
Low Power: 500 mW
+5 V Single Supply Operation
TTL Output Interface
Single or Demultiplexed Output Ports
APPLICATIONS
RGB Graphics Processing
High Resolution Video
Digital Data Storage Read Channels
Digital Communications
Digital Instrumentation
Medical Imaging
GENERAL DESCRIPTION
The AD9054 is an 8-bit monolithic analog-to-digital converter
optimized for high speed, low power, small size and ease of use.
With a 200 MSPS encode rate capability and full-power analog
bandwidth of 350 MHz, the component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, the AD9054
includes an internal +2.5 V reference and track-and-hold circuit.
The user provides only a +5 V power supply and an encode
clock. No external reference or driver components are required
for many applications.
AIN
AIN
ENCODE
ENCODE
FUNCTIONAL BLOCK DIAGRAM
VREF IN
VREF OUT
AD9054
؉2.5V REFERENCE
T/H
TIMING
QUANTIZER
8
ENCODE
LOGIC
DEMULTIPLEXER 8
DA7 – D A0
DB7 – D B0
VDD GND
DEMUX
DS DS
The AD9054’s encode input interfaces directly to TTL, CMOS
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual-channel or single-
channel digital outputs. The dual (demultiplexed) mode inter-
leaves ADC data through two 8-bit channels at one-half the
clock rate. Operation in demultiplexed mode reduces the speed
and cost of external digital interfaces while allowing the ADC to
be clocked to the full 200 MSPS conversion rate. In the single-
channel (nondemultiplexed) mode, all data is piped at the full
clock rate to the Channel A outputs.
Fabricated with an advanced BiCMOS process, the AD9054 is
provided in a space-saving 44-lead TQFP surface mount plastic
package (ST-44) and specified over the full industrial (–40°C to
+85°C) temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997






AD9054 Datasheet, Funktion
AD9054
EQUIVALENT CIRCUITS
AIN
VDD
AIN
DEMUX
300
17.5k
300
VDD
7.5k
Figure 3. Equivalent Analog Input Circuit
VDD
VREF IN
Figure 6. Equivalent DEMUX Input Circuit
VDD
DIGITAL
OUTPUTS
Figure 4. Equivalent Reference Input Circuit
ENCODE
OR DS
300
17.5k
300
VDD
ENCODE
OR DS
7.5k
Figure 7. Equivalent Digital Output Circuit
VDD
VREF
OUT
Figure 5. Equivalent ENCODE and Data Select Input Circuit
Figure 8. Equivalent Reference Output Circuit
–6– REV. 0

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AD9054 pdf, datenblatt
AD9054
When driven differentially, ENCODE and DS will accommo-
date differential signals centered between 1.5 V and 4.5 V with
a total differential swing 800 mV (VID 400 mV).
Note the 6-diode clock input protection circuitry in Figure 5.
This limits the differential input voltage to ~ ± 2.1 V. When the
diodes turn on, current is limited by the 300 series resistor.
Exceeding 2.1 V across the differential inputs will have no im-
pact on the performance of the converter, but be aware of the
clock signal distortion that may be produced by the nonlinear
impedance at the converter.
CLOCK
ENC
VIH D
CLOCK
ENC
VIC M
VIL D
VID
a. Driving Differential Inputs Differentially
CLOCK
0.1F
ENC
ENC
VIH D
VIC M
VIL D
VID
b. Driving Differential Inputs Single-Endedly
Figure 34. Input Signal Level Definitions
Single Port Mode
When operated in a Single Port mode (DEMUX = HIGH), the
timing of the AD9054 is similar to any high speed A/D Con-
verter (Figure 1).
A sample is taken on every rising edge of ENCODE, and the
resulting data is produced on the output pins following the
FOURTH rising edge of ENCODE after the sample was taken
(four pipeline delays). The output data are valid tPD after the
rising edge of ENCODE, and remain valid until at least tV after
the next rising edge of ENCODE.
The maximum clock rate is specified as 100 MSPS. This is
recommended because the guaranteed output data valid time
equals the Clock Period (1/fS) minus the Output Propagation
Delay (tPD) plus the Output Valid Time (tV), which comes to
4.8 ns at 100 MHz. This is about as fast as standard logic is able
to capture the data with reasonable design margins. The AD9054
will operate faster in single-channel mode if you are able to
capture the data.
When operating in Single-Channel Mode, the outputs at Port B
are held static in a random state.
Figure 35 shows the AD9054 used in single-channel output
mode. The analog input (±0.5 V) is ac coupled and the ENCODE
input is driven by a TTL level signal. The chip’s internal refer-
ence is used.
0.1F
1k
VIN
0.1F
VREF OUT
VREF IN
AIN
AD9054
AIN
+5V DEMUX
A PORT
DS DS ENC ENC
0.1F
CLOCK
NC
NC = NO CONNECT
Figure 35. Single Port Mode—AC-Coupled Input—Single-
Ended Encode
Dual Port Mode
In Dual Port Mode (DEMUX = LOW), the conversion results
are alternated between the two output ports (Figure 2). This
limits the data output rate at either port to 1/2 the conversion
rate (ENCODE), and supports conversion at up to 200 MSPS
with TTL/CMOS compatible interfaces. Dual Channel Mode is
required for guaranteed operation above 100 MSPS, but may be
enabled at any specified conversion rate.
The multiplexing is controlled internally via a clock divider,
which introduces a degree of ambiguity in the port assignments.
Figure 2 illustrates that, prior to synchronization, either Port A
or Port B may produce the even or odd samples. This is re-
solved by exercising the Data Sync (DS) control, a differential
input (identical to the ENCODE input), which facilitates opera-
tion at high speed.
At least once after power-up, and prior to using the conversion
data, the part needs to be synchronized by a falling edge (or a
positive-going pulse) on DS (observing setup and hold times
with respect to ENCODE). If the converter’s internal timing is
in conflict with the DS signal when it is exercised, then two data
samples (one on each port) are corrupted as the converter is
resynchronized. The converter then produces data with a
known phase relationship from that point forward.
Note that if the converter is already properly synchronized, the
DS pulse has no effect on the output data. This allows the con-
verter to be continuously resynchronized by a pulse at 1/2 the
ENCODE rate. This signal is often available within a system, as
it represents the master clock rate for the demultiplexed output
data. Of course, a single DS signal may be used to synchronize
multiple A/D converters in a multichannel system.
Applications that call for the AD9054 to be synchronized at
power-up or only periodically during calibration/reset (i.e., valid
data is not required prior to synchronization), need only be
concerned with the timing of the falling edge of DS. The falling
edge of DS must satisfy the setup time defined by Figure 2 and
–12–
REV. 0

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