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PDF AD9051 Data sheet ( Hoja de datos )
| Número de pieza | AD9051 | |
| Descripción | 10-Bit/ 60 MSPS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
60 MSPS Sampling Rate
9.3 Effective Number of Bits at fIN = 10.3 MHz
250 mW Total Power at 60 MSPS
Selectable Input Bandwidth of 50 MHz or 130 MHz
On-Chip T/H and Voltage Reference
Single 5 V Supply Voltage
5 V or 3 V Logic I/O Compatible
Input Range and Output Coding Options Available
APPLICATIONS
Medical Imaging
Digital Communications
Professional Video
Instrumentation
Set-Top Box
10-Bit, 60 MSPS
A/D Converter
AD9051
FUNCTIONAL BLOCK DIAGRAM
AINB
AIN
ENCODE
BWSEL 5V GND
5V
AD9051
IN OUT
REFERENCE
CIRCUITS
T/H
TIMING
SUM
AMP
ADC
DAC
ADC
DECODE
LOGIC
10
GENERAL DESCRIPTION
The AD9051 is a complete 10-bit monolithic sampling analog-
to-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only 5 V and an encode clock to
achieve 60 MSPS sample rates with 10-bit resolution.
The encode clock is TTL compatible and the digital outputs are
CMOS; both can operate with 5 V/3 V logic. The two-step
architecture used in the AD9051 is optimized to provide the
best dynamic performance available while maintaining low
power consumption.
A 2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on a state-of-the-art BiCMOS
process, the AD9051 is packaged in a space saving surface
mount package (SSOP) and is specified over the industrial tem-
perature range (–40°C to +85°C).
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113
© Analog Devices, Inc.,2010
1 page  
AD9051
ABSOLUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
Analog Input
3.126 (3.50)*
2.5
1.874 (1.50)*
*(BRS-2V Version)
Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND)
Voltage Level
Positive Full Scale + 1 LSB
Midscale
Negative Full Scale – 1 LSB
OR
(Out of Range)
1
0
1
Digital Output
MSB . . . LSB
1111111111
0111111111
0000000000
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9051 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. C
5 Page 
AD9051
Overdrive of the Analog Input
Special care was taken in the design of the analog input section
of the AD9051 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 1.875 V to
3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range compara-
tors detect when the analog input signal is out of this range and
the input buffer is clamped. The digital outputs are locked at
their maximum or minimum value (i.e., all “0” or all “1”). This
precludes the digital outputs changing to an invalid value when
the analog input is out of range.
The input is protected to one volt outside the power supply
rails. For nominal power (5 V and ground), the analog input
will not be damaged with signals from +5.5 V to –0.5 V.
Timing
The performance of the AD9051 is very insensitive to the duty
cycle of the clock. Pulsewidth variations of as much as ± 15% for
encode rates of 40 MSPS and ± 10% for encode rates of 60 MSPS
will cause no degradation in performance. (See Figure 17, SNR vs.
Duty Cycle.)
The AD9051 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (refer to Figure 1,
Timing Diagram). The length of the output data lines and
loads placed on them should be minimized to reduce tran-
sients within the AD9051; these transients can detract from
the converter’s dynamic performance.
Power Dissipation
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 60 MSPS,
analog input is –FS.
As shown in Figure 3, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. The loading
determines the power dissipated in the output stages.
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.
The dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to Using the AD9051, 3 V
System). The lower output swings minimize power consumption
as follows: (1/2 CLOAD × VDD2 × Update Rate).
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9051 (Pin 3, VREFOUT). In normal operation the internal
reference is used by strapping together Pins 3 and 4 of the
AD9051. The internal reference has 500 µA of extra drive cur-
rent that can be used for other circuits.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9051, which cannot be obtained by using the internal refer-
ence. For these applications, an external 2.5 V reference can be
used to connect to Pin 4 of the AD9051. The VREFIN requires
2 µA of drive current.
The input range can be adjusted by varying the reference
voltage applied to the AD9051. No appreciable degradation
in performance occurs when the reference is adjusted ± 5%.
The full-scale range of the ADC tracks reference voltage
changes linearly.
–10–
REV. C
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD9051.PDF ] | |
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