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AD9002 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9002
Beschreibung High Speed 8-Bit Monolithic A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD9002 Datasheet, Funktion
a
High Speed 8-Bit
Monolithic A/D Converter
AD9002
FEATURES
150 MSPS ENCODE Rate
Low Input Capacitance: 17 pF
Low Power: 750 mW
–5.2 V Single Supply
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Systems
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
GENERAL DESCRIPTION
The AD9002 is an 8-bit, high speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process that
allows operation at sampling rates in excess of 150 MSPS. Func-
tionally, the AD9002 is comprised of 256 parallel comparator
stages whose outputs are decoded to drive the ECL compatible
output latches.
An exceptionally wide, large signal, analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold. The
comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9002 provides an external hysteresis control pin that
can be used to optimize comparator sensitivity to further improve
performance. Additionally, the AD9002’s low power dissipation
of 750 mW makes it usable over the full extended temperature
range. The AD9002 also incorporates an overflow bit to indicate
overrange inputs. This overflow output can be disabled with the
overflow inhibit pin.
FUNCTIONAL BLOCK DIAGRAM
OVERFLOW
INH
ANALOG IN
+VREF
REFMID
–VREF
ENCODE
ENCODE
AD9002
R 256
OVERFLOW
R
255
BIT 8 (MSB)
D
E
BIT 7
RC
128
O
DL
BIT 6
IA
R/2
NT
GC
BIT 5
H
R/2 L
127 O
BIT 4
G
I
R C BIT 3
2 BIT 2
R
1
BIT 1 (LSB)
GND HYSTERESIS
–VS
The AD9002 is available in two grades, one with 0.5 LSB linearity
and one with 0.75 LSB linearity. Both versions are offered in an
industrial grade, –25°C to +85°C, packaged in a 28-lead DIP
and a 28-leaded JLCC. The military temperature range devices,
–55°C to +125°C, are available in a ceramic DIP package and
complies with MIL-STD-883 Class B.
REV. G
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD9002 Datasheet, Funktion
AD9002
APPLICATION INFORMATION
The AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL logic levels are temperature
compensated and are therefore compatible with the AD9002 (and
most other ECL device families) only over a limited temperature
range. To operate at the highest ENCODE rates, the supporting logic
around the AD9002 will need to be equally fast. Whichever
ECL logic family is used, special care must be exercised to keep
digital switching noise away from the analog circuits round
the AD9002. The two most critical items are digital supply
lines and digital ground return.
The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more tradi-
tional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10 resistor in series with the amplifier output.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compatible ENCODE signal (see
Figure 1). In applications where only a single-ended signal is avail-
able, the AD96685, a high speed, ECL voltage comparator, can
be employed to generate the differential signals. All ECL sig-
nals (including the overflow bit) should be terminated properly to
avoid ringing and reflection.
The AD9002 also incorporates a HYSTERESIS control pin
that provides from 0 mV to 10 mV of additional hysteresis in the
comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INH pin of the AD9002 determines how
the converter handles overrange inputs (AIN +VREF). In the
“enabled” state (floating at –5.2 V), the OVERFLOW INH out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW INH
output will be at logic LOW, and all other outputs will be at
logic HIGH for overrange inputs (nonreturn-to-zero operation).
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS
control pin). This level of performance is extremely important in
fault sensitive applications, such as digital radio (QAM).
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is par-
ticularly important in wide bandwidth applications, such as
pulse signature analysis, commonly performed in advanced
radar receivers.
LAYOUT SUGGESTIONS
Designs using the AD9002, such as all high speed devices,
must follow a few basic layout rules to ensure optimum perfor-
mance. Essentially, these guidelines are meant to avoid many
of the problems associated with high speed designs. The first
requirement is for a substantial ground plane around and
under the AD9002. Separate ground plane areas for the digital and
analog components may be useful, but these separate grounds
should be connected together at the AD9002 to avoid the
effects of ground loop currents.
The second area that requires an extra degree of attention involves
the three reference inputs, +VREF, REFMID, and –VREF. The
+VREF input and the –VREF input should both be driven from a
low impedance source (note that the +VREF input is typically
tied to analog ground). A low drift amplifier should provide
satisfactory results, even over an extended temperature range.
Adjustments at the REFMID input may be useful in improving the
integral linearity by correcting any reference ladder skews. The
application circuit shown below demonstrates a simple and
effective means of driving the reference circuit.
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system noise
on conversion accuracy. The power supply pins must also be
decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors are recommended.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical connec-
tions. Otherwise, aperture delay errors may degrade converter
performance at high frequencies.
1k
–15V
4k
ANALOG
INPUT
(0V TO 2V)
NYQUIST
FILTER
0.1F
AD741
100
2N3906
10
0.1F
1.5k
1.5k
50
40
AD9611
EQUAL
DISTANCE
–VREF +VREF
AIN
AIN
ENCODE
INPUT
(GROUND
THRESHOLD)
50
AD96685
AD9002
ENCODE
ENCODE
–5.2A –5.2D
OVERFLOW
D8 (MSB)
D7
D6
D5
D4
D3
D2
D1 (LSB)
0.01F
0.1F
0.1F 0.01F
Figure 5. Typical Application
–6– REV. G

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