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AD8842 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8842
Beschreibung CMOS TrimDAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 14 Seiten
AD8842 Datasheet, Funktion
a
FEATURES
Low Cost
Replaces 8 Potentiometers
50 kHz 4-Quadrant Multiplying Bandwidth
Low Zero Output Error
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
±3 V Output Swing
Midscale Preset, Zero Volts Out
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Vertical Deflection Amplitude Adjustment
Waveform Generation and Modulation
8-Bit Octal, 4-Quadrant
Multiplying, CMOS TrimDAC
AD8842
FUNCTIONAL BLOCK DIAGRAM
VDD
LD
SDI
CLK
DECODED
ADDRESS
8
LOGIC
DATA
48
SERIAL
REGISTER
8X 8
DAC
R
E
G
I
S
T
E
R
S
8
8
DAC A
G
AD8842
DAC H
G
VINA
VOUT A
VINH
VOUT H
GND
SDO PR
VSS
GENERAL DESCRIPTION
The AD8842 provides eight general purpose digitally controlled
voltage adjustment devices. The TrimDAC® capability allows
replacement of the mechanical trimmer function in new designs.
The AD8842 is ideal for ac or dc gain control of up to 50 kHz
bandwidth signals. The four-quadrant multiplying capability is
useful for signal inversion and modulation often found in video
vertical deflection circuitry.
Internally the AD8842 contains eight voltage output digital-to-
analog converters, each with separate voltage inputs. A new
current conveyor amplifier design performs the four-quadrant
multiplying function with a single amplifier at the output of the
current steering digital-to-analog converter. This approach of-
fers an improved constant input resistance performance versus
previous voltage switched DACs used in TrimDAC circuits,
eliminating the need for additional input buffer amplifiers.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire serial
input digital interface. Twelve data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 4 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. A serial data output pin
at the opposite end of the serial register allows simple daisy
chaining in multiple DAC applications without additional exter-
nal decoding logic.
TrimDAC is a registered trademark of Analog Devices, Inc.
The current conveyor amplifier is a patented circuit belonging to Analog
Devices, Inc.
The AD8842 consumes only 95 mW from ± 5 V power supplies.
For single 5 V supply applications consult the DAC-8841. The
AD8842 is pin compatible with the 1 MHz multiplying band-
width DAC8840. The AD8842 is available in 24-pin plastic
DIP and surface mount SOL-24 packages.
RR
VIN
VOUT
VOUT = VIN • (D/128 – 1)
Figure 1. Functional Circuit of One 4-Quadrant
Multiplying Channel
VIN REF
R
D VIN
256 R
(1- D) VIN
256 R
CURRENT CONVEYOR
AMPLIFIER
I1
VOUT
= VIN (D/128–1)
I2
R
Figure 2. Actual Current Conveyor Implementation of
Multiplying DAC Channel
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113






AD8842 Datasheet, Funktion
Table I. Serial Input Decode Table
LAST
FIRST
LSB
D0
D1
D2
D3
D4
D5
D6
MSB LSB
D7 A0
A1
A2
MSB
A3
DATA
ADDRESS
MSB
LSB
A3 A2 A1 A0 DAC UPDATED
0 0 0 0 NO OPERATION
0 0 0 1 DAC A
0 0 1 0 DAC B
0 0 1 1 DAC C
0 1 0 0 DAC D
•••
1 0 0 0 DAC H
1 0 0 1 NO OPERATION
•••
1 1 1 1 NO OPERATION
MSB
LSB
DAC OUTPUT VOLTAGE
D7 D6 D5 D4 D3 D2 D1 D0
VOUT = (D/128 –1) x VIN
0 0 0 0 0 0 0 0 –VIN
0 0 0 0 0 0 0 1 (1/128–1) x VIN
0 1 1 1 1 1 1 1 (127/128–1) x VIN
1 0 0 0 0 0 0 0 (128/128–1) x VIN = 0V; (PRESET VALUE)
1 0 0 0 0 0 0 1 (129/128–1) x VIN
1 1 1 1 1 1 1 0 (254/128–1) x VIN
1 1 1 1 1 1 1 1 (255/128–1) x VIN VIN
AD8842
Table II. Input Logic Control Truth Table
CLK
LD
PR Input Shift Register Operation
LL
L
XL
XΗ
XH
H No Operation
H Shift One Bit in from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18)
L All DAC Registers = 80H
H Load Serial Register Data into DAC(X) Register
X Serial Data Input Register Loading Disabled
*Data shifted into the SDI pin appears twelve clocks later at the SDO pin.
REV. A
–5–

6 Page









AD8842 pdf, datenblatt
AD8842
CLOCK
DATA
LD
CLK AD8842
#1
SDI
CODED
PACKAGE
ADDRESS
WR
ADDRESSS
DECODE
EN
LD
CLK AD8842
#2
SDI
LD
CLK
AD8842
#N
SDI
ANALOG CONNECTIONS OMITTED FOR CLARITY
Figure 31. Addressing Multiple AD8842 Packages
There is some digital feedthrough from the digital input pins.
Operating the clock only when the DAC registers require updat-
ing minimizes the effect of the digital feedthrough on the analog
signal channels. Measurements of DAC switch feedthrough
shown in the electrical characteristics table were accomplished
by grounding the VINx inputs and cycling the data codes be-
tween all zeros and all ones. Under this condition 5 nV-s of
feedthrough was measured on the output of the switched DAC
channel. An adjacent channel measured less than 1 nV-s of digi-
tal crosstalk. The digital feedthrough and crosstalk photographs
shown in the typical performance characteristics section display
these characteristics (Figures 15 and 17).
Figure 32 shows a three-wire interface for a single AD8842 that
easily cascades for multiple packages. This circuit topology often
called daisy chaining requires preformating all the serial data for
each package in the chain. In the case of the 3 packages shown a
36 bit data word must be completely clocked into all the
AD8842 serial data input registers then the LD strobe would
transfer the data bits into the DAC registers updating one DAC
in each package.
µC
PA0
PA1
PA2
DATA
CLOCK
LD
CLK
SDI DAC A
AD8842 #1
LD
SDO DAC H
VOU
VO
SDI DAC A
CLK
AD8842 #2
LD
SDO DAC H
CLK
SDI DAC A
AD8842 #3
LD
SDO DAC H
Figure 32. Three-Wire Interface Updates Multiple
AD8842s
REV. A
–11–

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