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PDF AD8804 Data sheet ( Hoja de datos )
| Número de pieza | AD8804 | |
| Descripción | 12 Channel/ 8-Bit TrimDACs with Power Shutdown | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 Watts Including IDD & IREF
Midscale Preset, AD8802
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SHDN
AD8802/AD8804
D11
D10
D9
D8
D7
SER
REG
EN
ADDR
DEC
D D0
8
D7
DAC
REG
#1
D0
R
D7
DAC
REG
#12
D0
R
DAC
1
DAC
12
GND
RS VREFL
(AD8802 ONLY) (AD8804 ONLY)
VDD
VREFH
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
100
TA = +25°C
ALL DIGITAL INPUTS
10 TIED TOGETHER
1.0 VDD = +5V
0.1
0.01
0.001
VDD = +3V
0.0001
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT VOLTAGE – Volts
Figure 7. Supply Current vs. Logic Input Voltage
80
60
VDD = +5V
ALL OUTPUTS SET
TO MIDSCALE (80H)
40
20
0
10 100 1k 10k 100k
FREQUENCY – Hz
Figure 8. Power Supply Rejection vs. Frequency
6V
100
4V 90
OUT
2V
0V
2V
5V 10
CS 0%
0V 0%
5V
5µs
VDD = +5V
VREF = +5V
TIME – 5µs/DIV
Figure 9. Large-Signal Settling Time
AD8802/AD8804
OUTPUT1: OOH → FFH
VDD = +5V
100
90
VREF = +5V
f = 1MHz
10
0%
10mV
200ns
TIME – 0.2µs/DIV
Figure 10. Adjacent Channel Clock Feedthrough
100
90
OUT1
5mV/DIV
CS
5V/DIV
10
0%
5mV
1µs
OUTPUT1: 7FH → 80H
VDD = +5V
VREF = +5V
5V
TIME – 1µs/DIV
Figure 11. Midscale Transition
0.01
0.005
VDD = +4.5V
VREF = +4.5V
SS = 176 PCS
VREFL = 0V
0
–0.005
–0.01
0
100 200 300 400 500
HOURS OF OPERATION AT 150°C
600
Figure 12. Zero-Scale Error Accelerated by Burn-In
REV. 0
–5–
5 Page 
AD8802/AD8804
; This 8051 µC subroutine loads an AD8802 or AD8804 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1
DATA
90H
DAC_VALUE
DATA
40H
DAC_ADDR
DATA
41H
LOOPCOUNT
DATA
43H
;
ORG
100H
LD_8804:
ORL
PORT1,#11110000B
CLR
PORT1.5
MOV
LOOPCOUNT,#4
MOV
A,DAC_ADDR
RR A
RR A
RR A
RR A
ACALL
SEND_SERIAL
MOV
LOOPCOUNT,#8
MOV
A,DAC_VALUE
ACALL
SEND_SERIAL
SETB
PORT1.5
RET
;SFR register for port 1
;DAC Value
;DAC Address (0 through 7)
;COUNT LOOPS
;arbitrary start
;set CLK, /CS and /SHDN high
;Set Chip Select low
;Address is 4 bits
;Get DAC address
;Rotate the DAC
;address to the Most
;Significant Bits (MSBs)
;
;Send the address
;Do 8 bits of data
;Send the data
;Set /CS high
;DONE
SEND_SERIAL:
RLC
MOV
CLR
SETB
DJNZ
RET;
END
A
PORT1.7,C
PORT1.6
PORT1.6
LOOPCOUNT,SEND_SERIAL
;Move next bit to carry
;Move data to SDI
;Pulse the
;CLK input
;Loop if not done
Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface
An MC68HC11-to-AD8802/AD8804 Interface
Like the 8051 µC, the MC68HC11 includes a dedicated serial
data port (labeled SPI). The SPI port provides an easy interface
to the AD8802/AD8804 (Figure 27). The interface uses three
lines of Port D for the serial data, and one or two lines from
Port C to control the SHDN and RS (AD8802 only) inputs.
MC68HC11*
(PD3) MOSI
(PD4) SCK
(PD5) SS
PC0
PC1
AD8802/
AD8804*
SDI
CLK
CS
SHDN
RS (AD8802 ONLY)
A software routine for loading the AD8802/AD8804 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8802/AD8804. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8802/AD8804’s CS is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8802/AD8804.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. An AD8802/AD8804-to-MC68HC11 Interface
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD8804.PDF ] | |
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