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AD8802 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8802
Beschreibung 12 Channel/ 8-Bit TrimDACs with Power Shutdown
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD8802 Datasheet, Funktion
a
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 Watts Including IDD & IREF
Midscale Preset, AD8802
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SHDN
AD8802/AD8804
D11
D10
D9
D8
D7
SER
REG
EN
ADDR
DEC
D D0
8
D7
DAC
REG
#1
D0
R
D7
DAC
REG
#12
D0
R
DAC
1
DAC
12
GND
RS VREFL
(AD8802 ONLY) (AD8804 ONLY)
VDD
VREFH
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD8802 Datasheet, Funktion
AD8802/AD8804
0.04
0.02
0
–0.02
x + 2σ
x
x – 2σ
VDD = +4.5V
VREF = +4.5V
SS = 176 PCS
–0.04
0
100 200 300 400 500
HOURS OF OPERATION AT 150°C
600
Figure 13. Full-Scale Error Accelerated by Burn-In
1.0
0.5
0
–0.5
x + 2σ
x
x – 2σ
VDD = +4.5V
VREF = +4.5V
CODE = 55H
SS = 176 PCS
–1.0
0
100 200 300 400 500
HOURS OF OPERATION AT 150°C
600
Figure 14. REF Input Resistance Accelerated by Burn-In
OPERATION
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC# = A3 × 8 + A2 × 4 + A1 × 2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6 µs (13 × 12 ×
30 ns). The exact timing requirements are shown in Figure 15.
Table I. Serial-Data Word Format
ADDR
DATA
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
211 210 29 28 27 26 25 24 23 22 21 20
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and VREF inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
1
SDI
0
CLK
1
0
1
CS
0
+5V
VOUT
0V
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
Figure 15a. Timing Diagram
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
SDI
(DATA IN)
1
0
CLK
CS
1
0
1
0
+5V
VOUT
0V
AX OR DX
tCH
AX OR DX
tDS
tDH
tCS1
tCSS
tCL tCSH
tCSW
tS
±1/2 LSB ERROR BAND
±1/2 LSB
Figure 15b. Detail Timing Diagram
RESET TIMING
1
RS
0
+5V
VOUT
2.5V
tRS
tS
±1 LSB ERROR BAND
±1 LSB
Figure 15c. Reset Timing Diagram
–6– REV. 0

6 Page









AD8802 pdf, datenblatt
AD8802/AD8804
*
* AD8802/AD8804 to M68HC11 Interface Assembly Program
*
* M68HC11 Register definitions
*
PORTC
EQU
$1003
Port C control register
* “0,0,0,0;0,0,RS/, SHDN/”
DDRC
EQU
$1007
Port C data direction
PORTD
EQU
$1008
Port D data register
* “0,0,/CS,CLK;SDI,0,0,0”
DDRD
EQU
$1009
Port D data direction
SPCR
EQU
$1028
SPI control register
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR
EQU
$1029
SPI status register
* “SPIF,WCOL,0,MODF;0,0,0,0”
SPDR
EQU
$102A
SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables:
SDI1 is encoded from 0H to 7H
* SDI2 is encoded from 00H to FFH
* AD8802/AD8804 requires two 8-bit loads; upper 4 bits
* of SDI1 are ignored. AD8802/AD8804 address bits in last
* four LSBs of SDI1.
*
SDI1
EQU
$00
SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0”
SDI2
EQU
$01
SDI packed byte 2 “DB7–DB4;DB3–DB0”
*
* Main Program
*
ORG
$C000
Start of user’s RAM in EVB
INIT
LDS
#$CFFF
Top of C page RAM
*
* Initialize Port C Outputs
*
LDAA
#$03
0,0,0,0;0,0,1,1
* /RS-Hi, /SHDN-Hi
STAA
PORTC
Initialize Port C Outputs
LDAA
#$03
0,0,0,0;0,0,1,1
STAA
DDRC
/RS and /SHDN are now enabled as outputs
*
* Initialize Port D Outputs
*
LDAA
#$20
0,0,1,0;0,0,0,0
* /CS-Hi,/CLK-Lo,SDI-Lo
STAA
PORTD
Initialize Port D Outputs
LDAA
#$38
0,0,1,1;1,0,0,0
STAA
DDRD
/CS,CLK, and SDI are now enabled as outputs
*
* Initialize SPI Interface
*
LDAA
#$53
STAA
SPCR
SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32
*
* Call update subroutine
*
BSR
UPDATE
Xfer 2 8-bit words to AD8402
JMP $E000
Restart BUFFALO
*
* Subroutine UPDATE
*
UPDATE PSHX
Save registers X, Y, and A
PSHY
PSHA
*
* Enter Contents of SDI1 Data Register
–12–
REV. 0

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