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PDF AD8801 Data sheet ( Hoja de datos )
| Número de pieza | AD8801 | |
| Descripción | Octal 8-Bit TrimDAC with Power Shutdown | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Octal 8-Bit TrimDAC
with Power Shutdown
AD8801/AD8803
FEATURES
Low Cost
Replaces Eight Potentiometers
Eight Individually Programmable Outputs
Three-Wire Serial Input
Power Shutdown ≤ 25 W Including IDD and IREF
Midscale Preset, AD8801
Separate VREFL Range Setting, AD8803
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Potentiometer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The AD8801/AD8803 provides eight digitally controlled dc
voltage outputs. This potentiometer divider TrimDAC® allows
replacement of the mechanical trimmer function in new designs.
The AD8801/AD8803 is ideal for dc voltage adjustment
applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8801 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8803 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of de-
vices with a limited allowable voltage control range.
FUNCTIONAL BLOCK DIAGRAM
(DACs 2–7 Omitted for Clarity)
VREFH
VREFL
VDD
GND
SDI
CLK
CS
AD8801/AD8803
1
DAC
SELECT
8
ADDRESS
3
11-BIT
SERIAL 8
LATCH
D
CK RS
8 8-BIT
LATCH
CK RS
8 8-BIT 8
LATCH
CK RS
VREFH
DAC 1 VOUT
VREFL
8
......
VREFH
DAC 8 VOUT
VREFL
8
O1
O8
RS SHDN
Internally the AD8801/AD8803 contain eight voltage output
digital-to-analog converters, sharing a common reference volt-
age input.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-par-
allel shift register that is loaded from a standard three-wire serial
input digital interface. Eleven data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 3 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. The AD8801/AD8803
consumes only 5 µA from 5 V power supplies. In addition, in
shutdown mode reference input current consumption is also re-
duced to 5 µA while saving the DAC latch settings for use after
return to normal operation.
The AD8801/AD8803 is available in 16-pin plastic DIP and the
1.5 mm height SO-16 surface mount packages.
See the AD8802/AD8804 for a twelve channel version of this product.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD8801/AD8803
For example, when VREFH = +5 V and VREFL = 0 V the follow-
ing output voltages will be generated for the following codes:
D VOX
Output State
(VREFH = +5 V, VREFL = 0 V)
255 4.98 V Full-Scale
128 2.50 V Half-Scale (Midscale Reset Value)
1
0.02 V
1 LSB
0
0.00 V
Zero-Scale
REFERENCE INPUTS (VREFH, VREFL)
The reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the VREFH pin is avail-
able to establish a user designed full-scale output voltage. The
external reference voltage can be any value between 0 and VDD
but must not exceed the VDD supply voltage. In the case of the
AD8803, which has access to the VREFL which establishes the
zero-scale output voltage, any voltage can be applied between
0 V and VDD. VREFL can be smaller or larger in voltage than
VREFH since the DAC design uses fully bidirectional switches as
shown in Figure 3. The input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55H, which is approximately 2 kΩ. When VREFH is greater than
VREFL, the REFL reference must be able to sink current out of
the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. The DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.
DAC OUTPUTS (O1–O8)
The eight DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. The distribu-
tion of ROUT from DAC to DAC typically matches within ± 1%.
However, device to device matching is process lot dependent
having a ± 20% variation. The change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all eight outputs are open circuited.
CS
CLK
SDI
SHDN
AD8801/AD8803
D10
D9
D8
D7
SER
...REG
EN
ADDR
DEC
D7
DAC
REG
#1
D0 R
... ... ...
DDA1ACC
... ...
D D0
8
D7
DAC
REG
#8
D0 R
DAC
8
VDD
VREFH
O1
O2
O3
O4
O5
O6
O7
O8
GND
RS VREFL
(AD8801 ONLY) (AD8803 ONLY)
Figure 4. Block Diagram
DIGITAL INTERFACING
The AD8801/AD8803 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 4 block diagram shows more detail of the internal digital cir-
cuitry. When CS is taken active low, the clock can load data into
the serial register on each positive clock edge, see Table II.
Table II. Input Logic Control Truth Table
CS CLK Register Activity
1 X No effect.
0P
Shifts Serial Register one bit loading the
next bit in from the SDI pin.
P X Data is transferred from the serial register
to the decoded DAC register. See Figure 5.
NOTE: P = positive edge, X = don’t care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail.
DAC 1
...CS DAC 2
ADDR
DECODE
DAC 8
CLK
SDI
SERIAL
REGISTER
Figure 5. Equivalent Control Logic
The target DAC register is loaded with the last eight bits of the se-
rial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. This applies to
digital input pins CS, SDI, RS, SHDN, CLK.
100Ω
LOGIC
Figure 6. Equivalent ESD Protection Circuit
Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 VDD value. This allows 5 V logic to interface directly to
the part when it is operated at 3 V.
REV. A
–5–
5 Page 
AD8801/AD8803
The subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0 opera-
tion. Next the DAC’s Chip Select input is set low to enable the
AD8801/AD8803. The DAC address is obtained from memory
location DAC_ADDR, adjusted to compensate for the 8051’s
serial data format, and moved to the serial buffer register. At
this point, serial data transmission begins automatically. When
all 8 bits have been sent, the Transmit Interrupt bit is set, and
the subroutine then proceeds to send the DAC value stored at
location DAC_VALUE. Finally the Chip Select input is re-
turned high, causing the appropriate AD8801/AD8803 output
voltage to change, and the subroutine ends.
The 8051 sends data out of its shift register LSB first, while the
AD8801/AD8803 require data MSB first. The subroutine there-
fore includes a BYTESWAP subroutine to reformat the data.
This routine transfers the MSB-first byte at location SHIFT1 to
an LSB-first byte at location SHIFT2. The routine rotates the
MSB of the first byte into the carry with a Rotate Left Carry in-
struction, then rotates the carry into the MSB of the second byte
with a Rotate Right Carry instruction. After 8 loops, SHIFT2
contains the data in the proper format.
The BYTESWAP routine in Listing 1 is convenient because the
DAC data can be calculated in normal LSB form. For example,
producing a ramp voltage on a DAC is simply a matter of re-
peatedly incrementing the DAC_VALUE location and calling
the LD_8801 subroutine.
If the µC’s hardware serial port is being used for other purposes,
the AD8801/AD8803 can be loaded by using the parallel port.
A typical parallel interface is shown in Figure 26. The serial data
is transmitted to the DAC via the 8051’s Port1.7 output, while
Port1.6 acts as the serial clock.
Software for the interface of Figure 26 is contained in Listing 2. The
subroutine will send the value stored at location DAC_VALUE to
the AD8801/AD8803 DAC addressed by location DAC_ADDR.
The program begins by setting the AD8801/AD8803’s Serial
Clock and Chip Select inputs high, then setting Chip Select low
to start the serial interface process. The DAC address is loaded
into the accumulator and three Rotate Right shifts are per-
formed. This places the DAC address in the 3 MSBs of the ac-
cumulator. The address is then sent to the AD8801/AD8803 via
the SEND_SERIAL subroutine. Next, the DAC value is loaded
into the accumulator and sent to the AD8801/AD8803. Finally,
the Chip Select input is set high to complete the data transfer.
; This 8051 µC subroutine loads an AD8801 or AD8803 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1
DATA
90H
DAC_VALUE
DATA
40H
DAC_ADDR
DATA
41H
LOOPCOUNT
DATA
43H
;
ORG
100H
LD_8803:
ORL
PORT1,#11110000B
CLR
PORT1.5
MOV
LOOPCOUNT,#3
MOV
A,DAC_ADDR
RR A
RR A
RR A
ACALL
SEND_SERIAL
MOV
LOOPCOUNT,#8
MOV
A,DAC_VALUE
ACALL
SEND_SERIAL
SETB
PORT1.5
RET
;SFR register for port 1
;DAC Value
;DAC Address (0 through 7)
;COUNT LOOPS
;arbitrary start
;set CLK, /CS and /SHDN high,
;Set Chip Select low
;Address is 3 bits
; Get DAC address
; Rotate the DAC
;address to the Most
;Significant Bits (MSBs)
;Send the address
;Do 8 bits of data
;Send the data
;Set /CS high
;DONE
SEND_SERIAL:
RLC
MOV
CLR
SETB
DJNZ
RET;
END
A
PORT1.7,C
PORT1.6
PORT1.6
LOOPCOUNT,SEND_SERIAL
;Move next bit to carry
;Move data to SDI
;Pulse the
; CLK input
;Loop if not done
Listing 2. Software for the 8051 to AD8801/AD8803 Parallel Port Interface
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD8801.PDF ] | |
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