|
|
PDF AD8612 Data sheet ( Hoja de datos )
| Número de pieza | AD8612 | |
| Descripción | Ultrafast 4 ns Single Supply Comparators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD8612 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
Data Sheet
FEATURES
4 ns propagation delay at 5 V
Single-supply operation: 3 V to 5 V
100 MHz input
Latch function
APPLICATIONS
High speed timing
Clock recovery and clock distribution
Line receivers
Digital communications
Phase detectors
High speed sampling
Read channel detection
PCMCIA cards
Zero-crossing detector
High speed analog-to-digital converter (ADC)
Upgrade for LT1394 and LT1016 designs
GENERAL DESCRIPTION
The AD8611/AD8612 are single and dual 4 ns comparators
with latch function and complementary output. The latch is not
functional if VCC is less than 4.3 V.
Fast 4 ns propagation delay makes the AD8611/AD8612 good
choices for timing circuits and line receivers. Propagation delays
for rising and falling signals are closely matched and tracked over
temperature. This matched delay makes the AD8611/AD8612
good choices for clock recovery because the duty cycle of the
output matches the duty cycle of the input.
Ultrafast, 4 ns
Single-Supply Comparators
AD8611/AD8612
PIN CONFIGURATIONS
V+ 1
8 QA
IN+ 2 AD8611 7 QA
IN– 3 TOP VIEW 6 GND
V– 4 (Not to Scale) 5 LATCH
Figure 1. 8-Lead Narrow Body SOIC
(R-8)
V+ 1
IN+ 2
IN– 3
V– 4
AD8611
TOP VIEW
(Not to Scale)
8 QA
7 QA
6 GND
5 LATCH
Figure 2. 8-Lead MSOP
(RM-8)
QA 1
QA 2
GND 3
LEA 4
V– 5
INA– 6
INA+ 7
14 QB
AD8612
TOP VIEW
(Not to Scale)
13 QB
12 GND
11 LEB
10 V+
9 INB–
8 INB+
Figure 3. 14-Lead TSSOP
(RU-14)
The AD8611 has the same pinout as the LT1016 and LT1394,
with lower supply current and a wider common-mode input
range, which includes the negative supply rail.
The AD8611/AD8612 are specified over the industrial temper-
ature range (−40°C to +85°C). The AD8611 is available in both
8-lead MSOP and narrow 8-lead SOIC surface-mount packages.
The AD8612 is available in a 14-lead TSSOP surface-mount
package.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2000–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Total Analog Supply Voltage
Digital Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Input Current
Storage Temperature Range
R, RU, RM Packages
Operating Temperature Range
Junction Temperature Range
R, RU, RM Packages
Lead Temperature Range (Soldering, 10 sec)
Rating
7.0 V
7.0 V
VCC +0.3 V to
VEE −0.3 V
±5 V
Indefinite
±5 mA
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
AD8611/AD8612
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 4.
Package Type
8-Lead SOIC (R)
8-Lead MSOP (RM)
14-Lead TSSOP (RU)
θJA1 θJC Unit
158 43 °C/W
240 43 °C/W
240 43 °C/W
1θJA is specified for the worst-case conditions, that is, a device in socket for
P-DIP and a device soldered in circuit board for SOIC and TSSOP.
ESD CAUTION
Rev. B | Page 5 of 20
5 Page 
Data Sheet
AD8611/AD8612
The AD8611 output has a typical output swing between ground
and 1 V below the positive supply voltage. Decreasing the output
load resistance to ground lowers the maximum output voltage
due to the increase in output current. Table 6 shows the typical
output high voltage vs. load resistance to ground.
Table 6. Maximum Output Voltage vs. Resistive Load
Output Load to Ground
V+ − VOUT, HI (typ)
300 Ω
1.5 V
500 Ω
1.3 V
1 kΩ 1.2 V
10 kΩ
1.1 V
>20 kΩ
1.0 V
Connecting a 500 Ω to 2 kΩ pull-up resistor to V+ on the
output helps increase the output voltage so that it is closer to the
positive rail; in this configuration, however, the output voltage
will not reach its maximum until 20 ns to 50 ns after the output
voltage switches. This is due to the R-C time constant between
the pull-up resistor and the output and load capacitances. The
output pull-up resistor cannot improve propagation delay.
The AD8611 is stable with all values of capacitive load; however,
loading an output with greater than 30 pF increases the
propagation delay of that channel. Capacitive loads greater than
500 pF also create some ringing on the output wave. Table 7 shows
propagation delay vs. several values of load capacitance. The
loading on one output of the AD8611 does not affect the
propagation delay of the other output.
Table 7. Propagation Delay vs. Capacitive Load
CL (pF)
tPD Rising (ns)
tPD Falling (ns)
<10 3.5
3.5
33 5
5
100 8
7
390 14.5
10
680 26
15
At or below approximately 4.1 V, the latch pin becomes
unresponsive and must normally be tied low for low VCC
operation.
INPUT STAGE AND BIAS CURRENTS
The AD8611 and AD8612 each use a bipolar PNP differential input
stage. This enables the input common-mode voltage range to
extend from within 2.0 V of the positive supply voltage to 200 mV
below the negative supply voltage. Therefore, using a single 5 V
supply, the input common-mode voltage range is −200 mV to
+3.0 V. Input common-mode voltage is the average of the voltages
at the two inputs. For proper operation, the input common-mode
voltage must be kept within the common-mode voltage range.
The input bias current for the AD8611/AD8612 is 4 μA,
which is the amount of current that flows from each input of
the comparator. This bias current goes to zero on an input that
is high and doubles on an input that is low, which is a characteristic
common to any bipolar comparator. Care must be taken in
choosing resistances to be connected around the comparator
because large resistors could significantly decrease the voltage
due to the input bias current.
The input capacitance for the AD8611/AD8612 is typically 3 pF.
This is measured by inserting a 5 kΩ source resistance in series
with the input and measuring the change in propagation delay.
USING HYSTERESIS
Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is undesirable
for the output to toggle between states when the input signal is
close to the switching threshold. Figure 24 shows a simple method
for configuring the AD8611 or AD8612 with hysteresis.
SIGNAL
COMPARATOR
R1
VREF
R2
USING THE LATCH
TO MAINTAIN A CONSTANT OUTPUT
CF
Figure 24. Configuring the AD8611/AD8612 with Hysteresis
With the VCC supply at a nominal 5 V, the latch input to the
AD8611/AD8612 can retain data at the output of the comparator.
When the latch voltage goes high, the output voltage remains in
its previous state, independent of changes in the input voltage.
The setup time for the AD8611/AD8612 is 0.5 ns and the hold
time is 0.5 ns. Setup time is defined as the minimum amount of
time the input voltage must remain in a valid state before the
latch is activated for the latch to function properly. Hold time is
defined as the amount of time the input must remain constant
after the latch voltage goes high for the output to remain latched
to its voltage.
The latch input is TTL and CMOS compatible, so a logic high is
a minimum of 2.0 V and a logic low is a maximum of 0.8 V. The
latch circuitry in the AD8611/AD8612 has no built-in
In Figure 24, the input signal is connected directly to the inverting
input of the comparator. The output is fed back to the noninverting
input through R1 and R2. The ratio of R1 to R1 + R2 establishes
the width of the hysteresis window, with VREF setting the center
of the window, or the average switching voltage. The QA or QB
output switches low when the input voltage is greater than VHI,
and does not switch high again until the input voltage is less
than VLO, as given in Equation 1:
( )VHI = V + − 1.5 VREF
R1
R1 + R2
+
VREF
(1)
VLO
= VREF
×
R2
R1 + R2
where V+ is the positive supply voltage.
hysteresis.
Rev. B | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD8612.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD8610 | (AD8610 / AD8620) Wide Bandwidth JFET Operational Amplifier | Analog Devices |
| AD8611 | Ultrafast 4 ns Single Supply Comparators | Analog Devices |
| AD8612 | Ultrafast 4 ns Single Supply Comparators | Analog Devices |
| AD8613 | (AD8613 - AD8619) Input/Output Operational Amplifiers | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |