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PDF AD8600 Data sheet ( Hoja de datos )
| Número de pieza | AD8600 | |
| Descripción | 16-Channel/ 8-Bit Multiplying DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8600 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
16-Channel, 8-Bit
Multiplying DAC
AD8600*
FUNCTIONAL BLOCK DIAGRAM
CS
EN
A3
A2
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W RS VDD1 LD VDD2
CONTROL
LOGIC
VREF VCC
ADDRESS
DECODE
16 x 8
INPUT
REGISTERS
16 x 8
DAC
REGISTERS
AD8600
16
8-BIT
DACS
DGND1
DGND2 DACGND VEE
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
GENERAL DESCRIPTION
The AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within
± 1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
*Patent pending.
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
R/W•CS•ADDR•EN VDD1
VDD2 LD•EN VREF
VCC
DB7...DB0
INPUT
REGISTER
DAC
REGISTER
R-2R
DAC
OX
RS
DGND2 RS DACGND
VEE
DGND1
R/W•CS•ADDRESS
Figure 1. Equivalent DAC Channel
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD8600
ABSOLUTE MAXIMUM RATINGS
(TA= +25°C unless otherwise noted)
VDD1 (Digital Supply) to GND . . . . . . . . . . . . . . –0.3 V, +7 V
VDD2 (DAC Buffer/Driver Supply) . . . . . . . . . . . . –0.3 V, +7 V
VCC (Analog Supply) to GND . . . . . . . . . . . . . . . –0.3 V, +7 V
VEE (Analog Supply) to GND . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
VDD2 to VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Short Circuit Duration
VOUT to GND or Power Supplies1 . . . . . . . . . . . . . . . Continuous
Digital Input/Output Voltage to GND . . . –0.3 V, VDD + 0.3 V
Thermal Resistance–Theta Junction-to-Ambient (θJA)
PLCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Package Power Dissipation . . . . . . . . . . . . . . . . (TJ – TA)/θJA
Maximum Junction Temperature TJ max . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
NOTE
1No more than four outputs may be shorted to power or GND simultaneously.
PIN CONFIGURATION
6 5 4 3 2 1 44 43 42 41 40
O6 7
O5 8
O4 9
O3 10
O2 11
O1 12
O0 13
VDD1 14
RS 15
DB0 16
DB1 17
AD8600
TOP VIEW
(Not to Scale)
39 O9
38 O10
37 O11
36 O12
35 O13
34 O14
33 O15
32 DGND1
31 LD
30 CS
29 EN
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
ORDERING GUIDE
Model
Package
Temperature Description
Package
Option
AD8600AP –40°C to +85°C 44-Lead PLCC P-44A
AD8600Chips +25°C
Die*
*For die specifications contact your local Analog Devices sales office.
The AD8600 contains 5782 transistors.
PIN DESCRIPTION
Pin No.
1
2
Name
NC
VREF
3 DACGND
4 VCC
5 VEE
6 O7
7 O6
8 O5
9 O4
10 O3
11 O2
12 O1
13 O0
14 VDD1
15 RS
16 DB0
17 DB1
18 DB2
19 DB3
20 DB4
21 DB5
22 DB6
23 DB7
24 A0
25 A1
26 A2
27 A3
28 R/W
29 EN
30 CS
31 LD
32 DGND1
33 O15
34 O14
35 O13
36 O12
37 O11
38 O10
39 O9
40 O8
41 VEE
42 VCC
43 DGND2
44 VDD2
Description
No Connection
Reference input voltage common
to all DACs.
DAC Analog Ground Return. Sets
analog zero-scale voltage.
Output Amplifier Positive Supply
Output Amplifier Negative Supply
DAC Channel Output No. 7
DAC Channel Output No. 6
DAC Channel Output No. 5
DAC Channel Output No. 4
DAC Channel Output No. 3
DAC Channel Output No. 2
DAC Channel Output No. 1
DAC Channel Output No. 0
Digital Logic Power Supply
Active Low Reset Input Pin
Data Bit Zero I/O (LSB)
Data Bit I/O
Data Bit I/O
Data Bit I/O
Data Bit I/O
Data Bit I/O
Data Bit I/O
Most Significant Data Bit I/O (MSB)
Address Bit Zero (LSB)
Address Bit
Address Bit
Most Significant Addr Bit (MSB)
Read/Write Select Control Input
Active Low Enable Clock Strobe
Chip Select Input
DAC Register Load Strobe
Digital Ground Input No. 1
DAC Channel Output No. 15
DAC Channel Output No. 14
DAC Channel Output No. 13
DAC Channel Output No. 12
DAC Channel Output No. 11
DAC Channel Output No. 10
DAC Channel Output No. 9
DAC Channel Output No. 8
Output Amplifier Negative Supply
Output Amplifier Positive Supply
Digital Ground Input No. 2
DAC Analog Supply Voltage
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8600 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
5 Page 
AD8600
Unipolar Output Operation
The AD8600 is configured to give unipolar operation. The full-
scale output voltage is equivalent to the reference input voltage
minus 1 LSB. The output is dependent upon the digital code
and follows Table III. The actual numbers given for the analog
output are calculated assuming a +2.5 V reference.
Table III. Unipolar Code Table
DAC
Binary Input
MSB LSB
Analog Output
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
+VREF (255/256) = +2.49 V
+VREF (129/256) = +1.26 V
+VREF (128/256) = +1.25 V
+VREF (127/256) = +1.24 V
+VREF (001/256) = +0.01 V
+VREF (000/256) = +0.00 V
Bipolar Output Operation
The AD8600 can be configured for bipolar operation with the
addition of an op amp for each output as shown in Figure 20.
The output will now have a swing of ± VREF, as detailed in Table
IV. This modification is only needed on those channels that re-
quire bipolar outputs. For channels which only require unipolar
output, no external amplifier is needed. The OP495 quad am-
plifier is chosen for the external amplifier because of its low
power, rail-to-rail output swing, and DC accuracy. Again, the
values calculated for the analog output are based upon an as-
sumed +2.5 V reference.
VREF
R1
10k
R1
10k
VREF
AD8600
+5V
1/4
OUTø OP495
–5V
VOUT
Figure 20. Circuit for Bipolar Output Operation
Table IV. Bipolar Code Table
DAC
Binary Input
MSB LSB Analog Output
1111 1111
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
+2 VREF (255/256) – VREF = +2.49 V
+2 VREF (129/256) – VREF = +0.02 V
+2 VREF (128/256) – VREF = +0.00 V
+2 VREF (127/256) – VREF = –0.02 V
+2 VREF (001/256) – VREF = –2.48 V
+2 VREF (000/256) – VREF = –2.50 V
Interfacing to the 68HC11 Microcontroller
The 68HC11 is a popular microcontroller from Motorola,
which is easily interfaced to the AD8600. The connections be-
tween the two components are shown in Figure 21. Port C of
the 68HC11 is used as a bidirectional input/output data port to
write to and read from the AD8600. Port B is used for address-
ing and control information. The bottom 4 LSBs of Port B are
the address, and the top 4 MSBs are the control lines (LD, CS,
EN, and R/W). The microcode for the 68 HC11 is shown in
Figure 22. The comments in the program explain the function
of each step. Three routines are included in this listing: read
from the AD8600, write to the AD8600, and a continuous loop
that generates a saw-tooth waveform. This loop is used in the
application below.
PC0–PC7
8
PB0–PB3
4
PB4
MOTOROLA
68HC11
PB5
PB6
GND
PB7
DB0–DB7
A0–A3
LD AD8600
EN
R/ W
CS
DGND1, DGND2
DACGND
DIGITAL GROUND
ANALOG GROUND
Figure 21. Interfacing the 68HC11 to the AD8600
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD8600.PDF ] | |
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