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AD8381 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8381
Beschreibung 6-Channel Output DecDriver Decimating LCD Panel Driver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
AD8381 Datasheet, Funktion
a Fast, High Voltage Drive, 6-Channel Output
DecDriver® Decimating LCD Panel Driver
AD8381
FEATURES
High Voltage Drive:
Rated Settling Time to within 1.3 V of Supply Rails
Output Overload Protection
High Update Rates:
Fast, 100 Ms/s 10-Bit Input Word Rate
Low Power Dissipation: 570 mW
Includes STBY Function
Voltage Controlled Video Reference (Brightness) and
Full-Scale (Contrast) Output Levels
3.3 V or 5 V Logic and 9 V to 18 V Analog Supplies
High Accuracy:
Laser Trimming Eliminates External Calibration
Flexible Logic:
INV Reverses Polarity of Video Signal
STSQ/XFR for Parallel AD8381 Operation in
12-Channel Systems
Drives Capacitive Loads:
27 ns Settling Time to 1% into 150 pF Load
Slew Rate 265 V/s with 150 pF Load
Available in 48-Lead LQFP
APPLICATIONS
LCD Analog Column Driver
FUNCTIONAL BLOCK DIAGRAM
DB (0:9)
STBY
BYP
E/O
R/L
CLK
STSQ
XFR
10 10
10
2-STAGE
LATCH
DAC
AD8381
10 10
2-STAGE
LATCH
DAC
BIAS
10 10
2-STAGE
LATCH
DAC
10 10
2-STAGE
LATCH
DAC
10 10
2-STAGE
LATCH
DAC
SEQUENCE
CONTROL
10 10
2-STAGE
LATCH
DAC
SCALING
CONTROL
VID0
VID1
VID2
VID3
VID4
VID5
VREFHI VREFLO
INV VMID
PRODUCT DESCRIPTION
The AD8381 provides a fast, 10-bit latched decimating digital
input, which drives six high voltage outputs. Ten-bit input
words are sequentially loaded into six separate high speed, bipolar
DACs. Flexible digital input format allows several AD8381s to be
used in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating and R/L controls the direction of loading as either
left-to-right or right-to-left. Six channels of high voltage
output drivers drive to within 1.3 V of the rail in rated settling
time. The output signal can be adjusted for brightness, signal
inversion, and contrast for maximum flexibility.
The AD8381 is fabricated on ADI’s proprietary, fast bipolar
24 V process, providing fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage precision drive
amplifiers on the same chip.
The AD8381 dissipates 570 mW nominal static power. The
STBY pin reduces power to a minimum, with fast recovery.
The AD8381 is offered in a 48-lead 7 mm ¥ 7 mm ¥ 1.4 mm
LQFP package and operates over the commercial temperature
range of 0C to 85C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD8381 Datasheet, Funktion
PIN CONFIGURATION
AD8381
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
DB0 2
DB1 3
DB2 4
DB3 5
DB4 6
DB5 7
DB6 8
DB7 9
DB8 10
DB9 11
NC 12
PIN 1
IDENTIFIER
AD8381
TOP VIEW
(Not to Scale)
36 VID0
35 AVCC0, 1
34 VID1
33 AGND1, 2
32 VID2
31 AVCC2, 3
30 VID3
29 AGND3, 4
28 VID4
27 AVCC4, 5
26 VID5
25 AGND5
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
1, 12, 19, 23, NC
24, 43–45
2–11
DB (0:9)
13 E/O
14 R/L
15 INV
16
17
18, 27, 31
35, 42
20
DGND
DVCC
AVCCx
STBY
21 BYP
22, 25, 29
33, 37, 41
26, 28, 30,
32, 34, 36
38
AGNDx
VID5, VID4, VID3,
VID2, VID1, VID0
VMID
39 VREFLO
40 VREFHI
46 STSQ
47 XFR
48 CLK
Function
No Connect
Description
Data Input
Even/Odd Select
Right/Left Select
Invert
Digital Supply Return
Digital Power Supply
Analog Power Supplies
10-Bit Data Input MSB = DB (9).
The active CLK edge is the rising edge when this input is held high,
and it is the falling edge when this input is held low.
Data is loaded sequentially on the rising edges of CLK when this input
is high and loaded on the falling edges when this input is low.
A new data loading sequence begins on the left, with Channel 0, when this
input is low, and on the right, with Channel 5, when this input is high.
When this pin is high, the analog output voltages are above VMID.
When low, the analog output voltages are below VMID.
This pin is normally connected to the analog ground plane.
Digital Power Supply.
Analog Power Supplies.
Standby
Bypass
Analog Supply Returns
When high, the internal circuits are debiased and the power
dissipation drops to a minimum.
A 0.1 mF capacitor connected between this pin and AGND ensures
optimum settling time.
These pins are normally connected to the analog ground plane.
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
Midpoint Reference
Full-Scale Reference
Full-Scale Reference
Start Sequence
Data Transfer
Clock
The voltage applied between this pin and AGND sets the midpoint
reference of the analog outputs. This pin is normally connected to VCOM.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
A new data loading sequence begins on the rising edge of CLK when
this input was high on the preceding rising edge of CLK and the E/O
input is held high.
A new data loading sequence begins on the falling edge of CLK when
this input was high on the preceding falling edge of CLK and the E/O
input is held low.
Data is transferred to the outputs on the immediately following falling
edge of CLK when this input is high on the rising edge of CLK.
Clock Input.
REV. B
–5–

6 Page









AD8381 pdf, datenblatt
AD8381
TRANSFER FUNCTION
The AD8381 has two regions of operation, selected by the INV
input, where the video output voltages are either above or below
a reference voltage, applied externally at the VMID input.
The transfer function defines the analog output voltage as the
function of the digital input code as follows:
VOUT = VMID ±VFS ¥ ÊËÁ1– 10n23ˆ¯˜
where:
n = input code
VFS = 2 ¥ (VREFHI – VREFLO)
VOUT (V)
AVCC
(VMID + VFS)
VOUTN(n)
INV = HIGH
VMID
(VMID – VFS)
AGND
0
VOUTP(n)
INV = LOW
INPUT CODE
1023
Figure 5. Transfer Function
The region over which the output voltage varies with input code
is selected by the INV input. When INV is low, the output volt-
age increases from (VMID – VFS), (where VFS = the full-scale
output voltage), to VMID as the input code increases from 0 to
1023. When INV is high, the output voltage decreases from
(VMID + VFS) to VMID with increasing input code.
For each value of input code there are then two possible values
of output voltage. When INV is low, the output is defined as
VOUTP(n) where n is the input code and P indicates the oper-
ating region where the slope of the transfer function is positive.
When INV is high, the output is defined as VOUTN(n) where N
indicates the operating region where the slope of the transfer
function is negative.
ACCURACY
To best correlate transfer function errors to image artifacts, the
overall accuracy of the AD8381 is defined by two parameters,
VDE and VCME.
VDE, the differential error voltage, measures the deviation of the
rms value of the output from the rms value of the ideal. It is depen-
dent on the difference between the output amplitudes VOUTN(n)
and VOUTP(n) at a particular code. The defining expression is
( )VDE
=
1
2
¥
VOUTN(n) – VOUTP(n)
ÊËÁVFS ¥ ÊËÁ1 – 10n23ˆ¯˜ˆ¯˜
where:
( )1
2
¥
VOUTN(n) – VOUTP(n)
is the rms value of the output.
(VFS ¥ (1 – n/1023)) is the rms value of the ideal.
VCME, the common-mode error voltage, measures the devia-
tion of the average value of the output from the average value of
the ideal. It is dependent on the average between the output
amplitudes VOUTN(n) and VOUTP(n) at a particular code.
The defining expression is:
( )VCME
=
1
2
¥
ÊËÁ
1
2
¥
VOUTN(n) +VOUTP(n)
VMIDˆ¯˜
where:
( )1
2
¥
VOUTN(n) +VOUTP(n)
is the average value of the output.
VMID is the average value of the ideal.
MAXIMUM FULL-SCALE OUTPUT VOLTAGE
The following conditions limit the range of usable output voltages:
The internal DACs limit the minimum allowed voltage at
the VMID input to 5.3 V.
The scale factor control loop limits the maximum full-scale
output voltage to 5.75 V.
The output amplifiers settle cleanly at voltages within 1.3 V
from the supply rails.
The common-mode range of the output amplifiers limit the
maximum value of VMID to AVCC – 3.
At any given valid value of VMID, the voltage required to reach
any one of the above limits defines the maximum usable full-
scale output voltage VFSMAX.
VFSMAX is the envelope in Figure 6. The valid range of VMID
is the shaded area.
VFS (V)
AVCC/2
AVCC/2–1.3
5.75
4.3
2
0
VALID VMID
5.3 7
AVCC–7
AVCC/2
VMID (V)
Figure 6. VFSMAX vs. VMID
AVCC–3
AVCC
REV. B
–11–

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