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PDF AD8328 Data sheet ( Hoja de datos )
| Número de pieza | AD8328 | |
| Descripción | 5 V Upstream Cable Line Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8328 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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FEATURES
Supports DOCSIS and EuroDOCSIS standards for reverse
path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 60 dBmV output
−57.5 dBc SFDR at 21 MHz
−54 dBc SFDR at 65 MHz
Output noise level @ minimum gain 1.2 nV/√Hz
Maintains 300 Ω output impedance Tx-enable and
Tx-disable condition
Upper bandwidth: 107 MHz (full gain range)
5 V supply operation
Supports SPI interfaces
APPLICATIONS
DOCSIS and EuroDOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GENERAL DESCRIPTION
The AD8328 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8328
ideally suited for MCNS-DOCSIS and EuroDOCSIS applications.
The gain of the AD8328 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8328 accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 2:1
transformer.
Distortion performance of −53 dBc is achieved with an output
level up to 60 dBmV at 65 MHz bandwidth over a wide
temperature range.
This device has a sleep mode function that reduces the quiescent
current to 2.6 mA and a full power-down function that reduces
power-down current to 20 μA.
The AD8328 is packaged in a low cost 20-lead LFCSP and
a 20-lead QSOP. The AD8328 operates from a single 5 V supply
and has an operational temperature range of −40°C to +85°C.
5 V Upstream
Cable Line Driver
AD8328
FUNCTIONAL BLOCK DIAGRAM
BYP
AD8328
VIN+
VIN–
DIFF
OR
SINGLE
INPUT
AMP
VERNIER
ZIN (SINGLE) = 800Ω
ZIN (DIFF) = 1.6kΩ
ATTENUATION
CORE
8
DECODE
POWER
AMP
ZOUT DIFF =
300Ω
VOUT+
VOUT–
8 POWER-DOWN
DATA LATCH
LOGIC
RAMP
8
SHIFT
REGISTER
GND
DATEN SDATA CLK
Figure 1.
TXEN SLEEP
–50
–52
VOUT = 60dBmV
–54 @ MAX GAIN,
THIRD HARMONIC
–56
–58
–60
–62
VOUT = 60dBmV
–64 @ MAX GAIN,
SECOND HARMONIC
–66
–68
–70
5
15 25 35 45
FREQUENCY (MHz)
55
Figure 2. Worst Harmonic Distortion vs. Frequency
65
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
SDATA
CLK
tDS
VALID DATA-WORD G1
MSB. . . .LSB
tC
tWH
VALID DATA-WORD G2
tES tEH
DATEN
TXEN
8 CLOCK CYCLES
GAIN TRANSFER (G1)
tOFF
tGS
GAIN TRANSFER (G2)
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 3. Serial Interface Timing
tON
SDATA MSB
CLK
VALID DATA BIT
MSB-1
tDS tDH
Figure 4. SDATA Timing
MSB-2
AD8328
Rev. A | Page 5 of 20
5 Page 
VCC
10µF
ZIN = 150Ω
VIN+
165Ω
VIN–
0.1µF
0.1µF
DATEN
SDATA
CLK
TXEN
SLEEP
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
AD8328
AD8328
1 GND
2
3
VCC
GND
4 GND
5
6
7
VIN+
VIN–
GND
8 DATEN
9 SDATA
10 CLK
QSOP
GND
VCC
TXEN
RAMP
VOUT+
VOUT–
BYP
NC
SLEEP
GND
20
19
18
17
16
15
14
13
12
11
0.1μF
0.1μF
0.1μF
TO DIPLEXER
ZIN = 75Ω
TOKO 458PT-1087
Figure 20. Typical Application Circuit
Table 6. Adjacent Channel Power
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
Adjacent Channel Symbol Rate (kSym/s)
160 320 640 1280
−58 −60 −63 −66
−58 −59 −60 −64
−60 −58 −59 −61
−62 −60 −59 −60
−64 −62 −60 −59
−66 −65 −62 −61
2560
−66
−66
−64
−61
−60
−59
5120
−64
−65
−65
−63
−61
−60
The output impedance of the AD8328 is 300 Ω, regardless
of whether the amplifier is in transmit enable or transmit
disable mode. This, when combined with a 2:1 voltage ratio
(4:1 impedance ratio) transformer, eliminates the need for
external back termination resistors. If the output signal is being
evaluated using standard 50 Ω test equipment, a minimum loss
75 Ω to 50 Ω pad must be used to provide the test circuit with
the proper impedance match. The AD8328 evaluation board
provides a convenient means to implement a matching attenuator.
Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω
resistor in the R16 placeholder allows testing on a 50 Ω system.
When using a matching attenuator, it should be noted that there
is a 5.7 dB of power loss (7.5 dB voltage) through the network.
POWER SUPPLY
The 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 μF tantalum capacitor located close to the AD8328. In
addition to the 10 μF capacitor, each VCC pin should be individually
decoupled to ground with ceramic chip capacitors located close
to the pins. The bypass pin, BYP, should also be decoupled. The
PCB should have a low impedance ground plane covering all
unused portions of the board, except in areas of the board
where input and output traces are in close proximity to the
AD8328 and the output transformer. All AD8328 ground pins
must be connected to the ground plane to ensure proper
grounding of all internal nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short minimizes parasitic capacitance and inductance. This is
most critical between the outputs of the AD8328 and the 2:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the
input and output traces should be adequately spaced to
minimize coupling (crosstalk) through the board. Following
these guidelines optimizes the overall performance of the
AD8328 in all applications.
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD8328.PDF ] | |
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