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PDF AD8307 Data sheet ( Hoja de datos )
| Número de pieza | AD8307 | |
| Descripción | Low Cost DC-500 MHz/ 92 dB Logarithmic Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Complete multistage logarithmic amplifier
92 dB dynamic range: −75 dBm to +17 dBm to −90 dBm
using matching network
Single supply of 2.7 V minimum at 7.5 mA typical
DC to 500 MHz operation, ±1 dB linearity
Slope of 25 mV/dB, intercept of −84 dBm
Highly stable scaling over temperature
Fully differential dc-coupled signal path
100 ns power-up time, 150 μA sleep current
APPLICATIONS
Conversion of signal level to decibel form
Transmitter antenna power measurement
Receiver signal strength indication (RSSI)
Low cost radar and sonar signal processing
Network and spectrum analyzers (to 120 dB)
Signal level determination down to 20 Hz
True decibel ac mode for multimeters
GENERAL DESCRIPTION
The AD8307 is the first logarithmic amplifier made available in
an 8-lead SOIC_N package. It is a complete 500 MHz monolithic
demodulating logarithmic amplifier based on the progressive
compression (successive detection) technique, providing a
dynamic range of 92 dB to ±3 dB law conformance and 88 dB to
a tight ±1 dB error bound at all frequencies up to 100 MHz. The
AD8307 is extremely stable and easy to use, requiring no significant
external components. A single-supply voltage of 2.7 V to 5.5 V
at 7.5 mA is needed. A fast acting CMOS-compatible control
pin can disable the AD8307 to a standby current of 150 μA.
The AD8307 operates over the industrial temperature range of
−40°C to +85°C and is available in an 8-lead SOIC package and
an 8-lead PDIP.
Low Cost, DC to 500 MHz, 92 dB
Logarithmic Amplifier
AD8307
FUNCTIONAL BLOCK DIAGRAM
VPS 7
7.5mA
AD8307
BAND GAP REFERENCE
AND BIASING
6 ENB
INP
+INP
8
INM 1 1.1kΩ
–INP 3
SIX 14.3dB 900MHz
AMPLIFIER STAGES
COM 2
NINE DETECTOR CELLS
SPACED 14.3dB
INPUT-OFFSET
COMPENSATION LOOP
5 INT
MIRROR
2µA
/dB
2
4 OUT
12.5kΩ
COM
3 OFS
Figure 1.
Table 1. Next Generation Upgrades for the AD8307
Device No. Product Description
AD8310 15 ns Response Time, Buffered Output
ADL5513
Lower Input Range (80 dB), Operation to 4 GHz,
Higher Power Consumption
AD8309 Higher Input Range (100 dB), Limiter Output
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1997–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8307
INM 1
8 INP
COM 2 AD8307 7 VPS
OFS 3 TOP VIEW 6 ENB
OUT 4 (Not to Scale) 5 INT
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 INM Signal Input Minus Polarity. Normally at VPOS/2.
2
COM
Common Pin (Usually Grounded).
3 OFS Offset Adjustment. External capacitor connection.
4 OUT Logarithmic (RSSI) Output Voltage. ROUT = 12.5 kΩ.
5 INT
Intercept Adjustment, ±3 dB. (See the Slope and Intercept Adjustments section.)
6 ENB CMOS-Compatible Chip Enable. Active when high.
7 VPS Positive Supply: 2.7 V to 5.5 V.
8 INP
Signal Input Plus Polarity. Normally at VPOS/2. Due to the symmetrical nature of the response, there is no special
significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ.
Rev. E | Page 5 of 24
5 Page 
Data Sheet
again A times larger and VOUT has increased to (3A − 2)EK, that
is, by another linear increment of (A − 1)EK.
Further analysis shows that right up to the point where the input to
the first cell is above the knee voltage, VOUT changes by (A − 1)EK
for a ratio change of A in VIN. This can be expressed as a certain
fraction of a decade, which is simply log10(A). For example,
when A = 5, a transition in the piecewise linear output function
occurs at regular intervals of 0.7 decade (log10(A), or 14 dB
divided by 20 dB). This insight immediately allows the user to
write the volts per decade scaling parameter, which is also the
scaling voltage, VY, when using base 10 logarithms, as
VY
Linear Change in VOUT
Decades Change in VIN
A 1EK
log10(A)
(4)
Note that only two design parameters are involved in determining
VY, namely, the cell gain A and the knee voltage, EK, while N,
the number of stages, is unimportant in setting the slope of the
overall function. For A = 5 and EK = 100 mV, the slope would be
a rather awkward 572.3 mV per decade (28.6 mV/dB). A well
designed log amp has rational scaling parameters.
The intercept voltage can be determined by using two pairs of
transition points on the output function (consider Figure 24).
The result is
VX
EK
A(N 1/A 1)
(5)
For the case under consideration, using N = 6, calculate VZ =
4.28 μV. However, be careful about the interpretation of this
parameter, because it was earlier defined as the input voltage at
which the output passes through zero (see Figure 21). Clearly, in
the absence of noise and offsets, the output of the amplifier chain
shown in Figure 23 can be zero when, and only when, VIN = 0.
This anomaly is due to the finite gain of the cascaded amplifier,
which results in a failure to maintain the logarithmic
approximation below the lin-log transition (labeled 1 in Figure 24).
Closer analysis shows that the voltage given by Equation 5
represents the extrapolated, rather than actual, intercept.
DEMODULATING LOG AMPS
Log amps based on a cascade of A/1 cells are useful in baseband
applications because they do not demodulate their input signal.
However, baseband and demodulating log amps alike can be
made using a different type of amplifier stage, called an A/0 cell.
Its function differs from that of the A/1 cell in that the gain
above the knee voltage EK falls to zero, as shown by the solid
line in Figure 25. This is also known as the limiter function, and
a chain of N such cells are often used to generate hard-limited
output in recovering the signal in FM and PM modes.
AD8307
AEK
A/0
SLOPE = 0
tanh
SLOPE = A
0
EK
INPUT
Figure 25. A/0 Amplifier Functions (Ideal and Tanh)
The AD640, AD606, AD608, AD8307, and various other Analog
Devices, Inc., communications products incorporating a logarith-
mic intermediate frequency (IF) amplifier all use this technique.
It becomes apparent that the output of the last stage can no longer
provide the logarithmic output because this remains unchanged
for all inputs above the limiting threshold, which occurs at VIN =
EK/AN−1. Instead, the logarithmic output is now generated by
summing the outputs of all the stages. The full analysis for this
type of log amp is only slightly more complicated than that of
the previous case. It is readily shown that, for practical purposes,
the intercept voltage, VX, is identical to that given in Equation 5,
while the slope voltage is
VY
AEK
log10 A
(6)
Preference for the A/0 style of log amp over one using A/1 cells
stems from several considerations. The first is that an A/0 cell
can be very simple. In the AD8307, it is based on a bipolar
transistor differential pair, having resistive loads, RL, and an
emitter current source, IE. This exhibits an equivalent knee
voltage of EK = 2 kT/q and a small signal gain of A = IERL/EK.
The large signal transfer function is the hyperbolic tangent (see
the dashed line in Figure 25). This function is very precise, and
the deviation from an ideal A/0 form is not detrimental. In fact,
the rounded shoulders of the tanh function result in a lower
ripple in the logarithmic conformance than that obtained using
an ideal A/0 function.
An amplifier composed of these cells is entirely differential in
structure and can thus be rendered very insensitive to disturbances
on the supply lines and, with careful design, to temperature
variations. The output of each gain cell has an associated
transconductance (gm) cell that converts the differential output
voltage of the cell to a pair of differential currents, which are
summed simply by connecting the outputs of all the gm (detector)
stages in parallel. The total current is then converted back to a
voltage by a transresistance stage to generate the logarithmic
output. This scheme is depicted in single-sided form in Figure 26.
Rev. E | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD8307.PDF ] | |
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