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AD8075 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8075
Beschreibung G = +1 and +2 Triple Video Buffers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 15 Seiten
AD8075 Datasheet, Funktion
a
FEATURES
Dual Supply ؎5 V
High-Speed Fully Buffered Inputs and Outputs
600 MHz Bandwidth (–3 dB) 200 mV p-p
500 MHz Bandwidth (–3 dB) 2 V p-p
1600 V/s Slew Rate, G = +1
1350 V/s Slew Rate, G = +2
Fast Settling Time: 4 ns
Low Supply Current: <30 mA
Excellent Video Specifications (RL = 150 ):
Gain Flatness of 0.1 dB to 50 MHz
0.01% Differential Gain Error
0.01؇ Differential Phase Error
“All Hostile“ Crosstalk
–80 dB @ 10 MHz
–50 dB @ 100 MHz
High “OFF” Isolation of 90 dB @ 10 MHz
Low Cost
Fast Output Disable Feature
APPLICATIONS
RGB Buffer in LCD and Plasma Displays
RGB Driver
Video Routers
500 MHz, G = +1 and +2 Triple
Video Buffers with Disable
AD8074/AD8075
FUNCTIONAL BLOCK DIAGRAM
AD8074 /AD8075
OE 1
16 VCC
DGND 2
IN2 3
G=
+1/+2
15 VCC
14 OUT2
AGND 4
IN1 5
G=
+1/+2
13 VEE
12 OUT1
AGND 6
IN0 7
G=
+1/+2
11 VCC
10 OUT0
VEE 8
9 VEE
PRODUCT DESCRIPTION
The AD8074/AD8075 are high-speed triple video buffers with
G = +1 and +2 respectively. They have a –3 dB full signal band-
width in excess of 450 MHz, along with slew rates in excess of
1400 V/µs. With better than –80 dB of all hostile crosstalk and
90 dB isolation, they are useful in many high-speed applica-
tions. The differential gain and differential phase error are 0.01%
and 0.01°. Gain flatness of 0.1 dB up to 50 MHz makes the
AD8074/AD8075 ideal for RGB buffering or driving. They
consume less than 30 mA on a ± 5 V supply.
Both devices offer a high-speed disable feature that allows the
outputs to be put into a high impedance state. This allows the
building of larger input arrays while minimizing “OFF” chan-
nel output loading. The AD8074/AD8075 are offered in a
16-lead TSSOP package.
Table I. Truth Table
OE OUT0, 1, 2
0 IN0, IN1, IN2
1 High Z
Rev. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2001–2011 Analog Devices, Inc. All rights reserved.






AD8075 Datasheet, Funktion
AD8074/AD8075
20
30
40
50
60
70 RL = 1k
80
90
100
110
0.1
RL = 150
1 10 100
FREQUENCY MHz
1000
TPC 11. AD8074 Off Isolation vs. Frequency
10
0
10
20
30
40
50
60
70
80
0.1
PSRR
+PSRR
1 10 100
FREQUENCY MHz
TPC 12. AD8074 PSRR vs. Frequency
1000
350
300
250
200
150
100
50
0
10 100 1k 10k 100k 1M
FREQUENCY Hz
TPC 13. AD8074 Voltage Noise vs. Frequency
20
30
40
50
60
70 RL = 1k
80
90 RL = 150
100
110
0.1
1 10 100
FREQUENCY MHz
1000
TPC 14. AD8075 Off Isolation vs. Frequency
20
10
0
10
+PSRR
20
PSRR
30
40
50
60
70
0.1
1 10 100
FREQUENCY MHz
1000
TPC 15. AD8075 PSRR vs. Frequency
400
350
300
250
200
150
100
50
0
10 100 1k 10k 100k 1M
FREQUENCY Hz
TPC 16. AD8075 Voltage Noise vs. Frequency
–6– Rev. B

6 Page









AD8075 pdf, datenblatt
AD8074/AD8075
Each of the six outputs has a 75 series resistor that is used to
reverse-terminate the output transmission line. The correspond-
ing outputs are then wired in parallel and delivered to the output
cable. The termination resistors in this position help to isolate
the off capacitance of the disabled devices outputs from loading
the enabled devices outputs. The gain-of-two of the AD8075
compensates for the signal halving that occurs as a result of the
output terminations.
A select signal is provided directly to the OE of the second
AD8075 and an inverted version is used to drive the other devices
OE. This will ensure that only one device is active at a time. Since
there is a total of 150 in series between any two outputs, it is
not essential to be overly concerned about the exact timing of
the making and breaking of the enable signals.
Additional inputs can easily be added to the circuit shown to
make wider multiplexers. The outputs of all of the devices will
be wired in parallel, and the logic must allow that only one output
be enabled at a time.
If it is desired to make a triple 3:1 multiplexer, a triple 2:1 mul-
tiplexer, like the AD8185 can be used along with the AD8075.
The same general guidelines for input and output treatment
should be followed and the logic must perform the proper function.
If it is desired to design such a multiplexer at unity gain, the
AD8074 should be used. For a triple 3:1 multiplexer, an
AD8183 (triple 2:1 mux) can be combined with an AD8074 to
provide this function.
Layout and Grounding
The AD8074 and AD8075 are extreme bandwidth, high-slew-rate
devices that are designed to drive up to the highest resolution
monitors and provide excellent resolution. To realize their full
performance potential, it is essential to adhere to the best prac-
tices of high-speed PCB layout.
A major area of focus should be the power distribution system.
There should be a full ground plane that provides the reference
and return paths for both the inputs and outputs. The ground
also provides isolation between the input signals to minimize the
crosstalk. This ground plane should cover as wide an area as
possible and be minimally interrupted in order to keep its
impedance to a minimum.
The power planes should also be as broad as possible to provide
minimal inductance, which is required for high-slew-rate sig-
nals. These power planes layers should be spaced closely to the
ground plane to increase the interplane capacitance between the
supplies and ground.
Each supply pin should be bypassed with a low inductance
0.1 µF ceramic capacitance with minimal excess circuit length
to minimize the series impedance. A 25 µF tantalum electro-
lytic capacitor will supply a charge reservoir for lower frequency,
high-amplitude transitions.
The input and output signals should be run as directly as pos-
sible in order to minimize the effects of parasitics. If they must
run over a longer distance of more than a few centimeters, con-
trolled impedance PCB traces should be used to minimize the
effect of reflections due to mismatches in impedance and the
proper termination should be provided.
To avoid excess crosstalk, the above recommendations should
be followed carefully. The power system and signal routing are
the most important aspects of preventing excess crosstalk.
Beyond these techniques, shielding can be provided by ground
traces between adjacent signals, especially those that travel
parallel over long distances.
–12–
Rev. B

12 Page





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