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ADP3605 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3605
Beschreibung 120 mA Switched Capacitor Voltage Inverter with Regulated Output
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
ADP3605 Datasheet, Funktion
a
120 mA Switched Capacitor
Voltage Inverter with Regulated Output
ADP3605
FEATURES
Fully Regulated Output Voltage (–3 V and Adjustable)
High Output Current: 120 mA
Output Accuracy: ؎3%
250 kHz Switching Frequency
Low Shutdown Current: 2 A Typical
Input Voltage Range from 3 V to 6 V
SO-8 and RU-14 Packages
–40؇C to +85؇C Ambient Temperature Range
APPLICATIONS
Voltage Inverters
Voltage Regulators
Computer Peripherals and Add-On Cards
Portable Instruments
Battery Powered Devices
Pagers and Radio Control Receivers
Disk Drives
Mobile Phones
FUNCTIONAL BLOCK DIAGRAM
CP+
CP
VIN
S PD
S1
ADP3605
SND
S2
DNS
S3
B
DNS
S4
VOUT
OSC
SD CLOCK
GEN
FEEDBACK
CONTROL
LOOP
VSENSE
GND
GENERAL DESCRIPTION
The ADP3605 is a 120 mA regulated output switched capacitor
voltage inverter. It provides a regulated output voltage with
minimum voltage loss and requires a minimum number of ex-
ternal components. In addition, the ADP3605 does not require
the use of an inductor.
Pin-for-pin and functionally compatible with the ADP3604, the
internal oscillator of the ADP3605 runs at 500 kHz nominal
frequency which produces an output switching frequency of
250 kHz. This allows for the use of smaller charge pump and
filter capacitors.
The ADP3605 provides an accuracy of ± 3% with a typical shut-
down current of 2 µA. It can also operate from a single positive
input voltage as low as 3 V. The ADP3605 is offered with the
regulation fixed at –3 V or adjustable via external resistors over
a –3 V to –6 V range.
VIN
+
* CIN
4.7F
*CP +
4.7F
VIN VOUT
CP+
ADP3605-3
–3.0V
* CO
+ 4.7F
CP
OFF
SD
ON
0
GND
VSENSE
*FOR BEST PERFORMANCE, 10F IS RECOMMENDED
CP : SPRAGUE, 293D475X0010B2W
CIN, CO: TOKIN, 1E475ZY5UC205F
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






ADP3605 Datasheet, Funktion
ADP3605
Pump Capacitor
The ADP3605 alternately charges CP to the input voltage when
CP is switched in parallel with the input supply, and then trans-
fers charge to CO when CP is switched in parallel with CO.
During the time CP is charging, the peak current is approxi-
mately two times the output current.
During the time CP is delivering charge to CO, the supply cur-
rent drops down to about 3 mA.
A low ESR capacitor has much greater impact on performance
for CP than CO since current through CP is twice the CO cur-
rent. Therefore, the voltage drop due to CP is about four times
the ESR of CP times the load current. While the ESR of CO
affects the output ripple voltage, the voltage drop generated by
the ESR of CP, combined with the voltage drop due to the output
source resistance, determines the maximum available VOUT.
10
ALUMINUM
1.0
CERAMIC
TANTALUM
0.1
ORGANIC SEMIC
0.01
–50
0 50
TEMPERATURE – ؇C
Figure 13. ESR vs. Temperature
100
100
ADP3605-3
80
60
150m
40
100m
20
50m
0
0 20 40 60 80 100 120 140 160
CAPACITANCE – F
Figure 14. Output Ripple Voltage (mV) vs. Capacitance
and ESR
Improved Load Regulation
In most applications, the IR drop from printed circuit board
traces is not critical. VSENSE should be connected to the output
at a convenient PCB location close to the load. However, if a
reduction in IR drop or improvement in load regulation is de-
sired, the sense line can be used to monitor the output voltage
at the load. To avoid excessive noise pickup, keep the VSENSE
line as short as possible and away from any noisy line.
Shutdown Mode
The ADP3605’s output can be disabled by pulling the SD pin
(Pin 4) high to a TTL/CMOS logic compatible level which will
stop the internal oscillator. In shutdown mode, the quiescent
current is reduced to 2 µA (typical). Applying a digital low level
or tying the SD Pin to ground will turn on the output. If the
shutdown feature is not used, Pin 4 should be tied to the
ground pin.
Power Dissipation
The power dissipation of the ADP3605 circuit must be limited
such that the junction temperature of the device does not exceed
the maximum junction temperature rating. Total power dissipa-
tion is calculated as follows:
P = (VIN –|VOUT|) IOUT + (VIN) IS
Where IOUT and IS are output current and supply current, VIN
and VOUT are input and output voltages respectively.
For example: assuming worst case conditions, VIN = 6 V,
VOUT = –2.9 V, IOUT = 120 mA and IS = 5 mA. Calculated
device power dissipation is:
P (6 V–|–2.9 V|)(0.12) + (6 V)(0.005 A) = 402 mW
This is far below the 660 mW power dissipation capability of the
ADP3605 in SO-8 or 600 mW in RU-14
General Board Layout Guidelines
Since the ADP3605’s internal switches turn on and off very fast,
good PC board layout practices are critical to ensure optimal
operation of the device. Improper layouts will result in poor load
regulation, especially under heavy loads. Following these simple
layout guidelines will improve output performance.
1. Use adequate ground and power traces or planes.
2. Use single point ground for device ground and input and
output capacitor grounds.
3. Keep external components as close to the device as possible.
4. Use short traces from the input and output capacitors
to the input and output pins respectively.
–6– REV. A

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