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ADP3413JR Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3413JR
Beschreibung Dual Bootstrapped MOSFET Driver with Output Disable
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
ADP3413JR Datasheet, Funktion
a
Dual Bootstrapped MOSFET Driver
with Output Disable
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Pulse-by-Pulse Disable Control
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
GENERAL DESCRIPTION
The ADP3413 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped, and is designed to handle the high-voltage
slew rate associated with floatinghigh-side gate drivers.
The ADP3413 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The OD pin provides high speed control to quickly turn off
both gate drives.
The ADP3413 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
ADP3413
IN
7V
VCC
ADP3413
FUNCTIONAL BLOCK DIAGRAM
VCC
BST
IN
OD 3
OVERLAP
PROTECTION
CIRCUIT
ADP3413
PGND
DRVH
SW
DRVL
12V
D1
BST
CBST
DRVH
Q1
SW
1V
OD 3
DELAY
+1V
DRVL
PGND
Q2
REV. 0
Figure 1. General Application Circuit
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






ADP3413JR Datasheet, Funktion
ADP3413
THEORY OF OPERATION
The ADP3413 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side FETs. Each driver
is capable of driving a 3 nF load.
A more detailed description of the ADP3413 and its features
follows. Refer to the Functional Block Diagram.
Low-Side Driver
The low-side driver is designed to drive low RDS(ON) N-channel
MOSFETs. The maximum output resistance for the driver is
3.5 for sourcing and 2.5 for sinking gate current. The
low output resistance allows the driver to have 30 ns rise
and fall times into a 3 nF load. The bias to the low-side driver is
internally connected to the VCC supply and PGND.
When the driver is enabled, the drivers output is 180 degrees
out of phase with the PWM input. When the ADP3413 is dis-
abled, the low-side gate is held low.
High-Side Driver
The high-side driver is designed to drive a floating low RDS(ON)
N-channel MOSFET. The maximum output resistance for the
driver is 3.5 for sourcing and 2.5 for sinking gate cur-
rent. The low output resistance allows the driver to have 30 ns
rise and fall times into a 3 nF load. The bias voltage for the
high-side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3413 is starting up, the SW pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high-side
driver will begin to turn the high-side MOSFET, Q1, ON by
pulling charge out of CBST. As Q1 turns ON, the SW pin will
rise up to VIN, forcing the BST pin to VIN + VC(BST), which is
enough gate to source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt-
age at the SW pin. When the low-side MOSFET, Q2, turns
ON, the SW pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again.
The high-side drivers output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
Overlap Protection Circuit
The Overlap Protection Circuit (OPC) prevents both of the main
power switches, Q1 and Q2, from being ON at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that can
occur during their ON-OFF transitions. The Overlap Protection
Circuit accomplishes this by adaptively controlling the delay from
Q1s turn OFF to Q2s turn ON, and by internally setting the
delay from Q2s turn OFF to Q1s turn ON.
To prevent the overlap of the gate drives during Q1s turn OFF
and Q2s turn ON, the overlap circuit monitors the voltage at the
SW pin. When the PWM input signal goes low, Q1 will begin to
turn OFF (after a propagation delay), but before Q2 can turn ON
the overlap protection circuit waits for the voltage at the SW pin
to fall from VIN to 1 V. Once the voltage on the SW pin has fallen
to 1 V, Q2 will begin turn ON. By waiting for the voltage on the
SW pin to reach 1 V, the overlap protection circuit ensures that
Q1 is OFF before Q2 turns on, regardless of variations in tem-
perature, supply voltage, gate charge, and drive current.
To prevent the overlap of the gate drives during Q2s turn OFF
and Q1s turn ON, the overlap circuit provides a internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn OFF (after a propagation delay), but before
Q1 can turn ON the overlap protection circuit waits for the
voltage at DRVL to drop to around 10% of VCC. Once the
voltage at DRVL has reached the 10% point, the overlap protec-
tion circuit will wait for a 20 ns typical propagation delay. Once
the delay period has expired, Q1 will begin turn ON.
Output Disable
The disable input is used to turn off the buck converter. If the
circuits running off of the buck converter are not needed, the
ADP3413 can be shutdown to conserve power. When the OD
pin is low, the ADP3413 is disabled. The DRVH and DRVL
outputs are forced low, turning the buck converter OFF.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (VCC) of the ADP3413, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size and can be obtained from
the following vendors:
Murata GRM235Y5V106Z16 www.murata.com
Taiyo-
Yuden EMK325F106ZF
www.t-yuden.com
Tokin C23Y5V1C106ZP
www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3413.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST) and a
Schottky diode, as shown in Figure 1. Selection of these compo-
nents can be done after the high-side MOSFET has been chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 volts. A minimum
50 V rating is recommended. The capacitance is determined
using the following equation:
CBST
=
QGATE
VBST
where, QGATE is the total gate charge of the high-side MOSFET,
and VBST is the voltage droop allowed on the high-side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot-
strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high-side MOSFET. The bootstrap diode must have a mini-
mum 40 V rating to withstand the maximum battery voltage
plus 5 V. The average forward current can be estimated by:
I F(AVG) QGATE × f MAX
where fMAX is the maximum switching frequency of the control-
ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 5 V
supply, and the ESR of CBST.
–6– REV. 0

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