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ADP3404 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3404
Beschreibung GSM Power Management System
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADP3404 Datasheet, Funktion
a
GSM Power Management System
ADP3404
FEATURES
Handles all GSM Baseband Power Management
Functions
Four LDOs Optimized for Specific GSM Subsystems
Charges Back-Up Capacitor for Real-Time Clock
Charge Pump and Logic Level Translators for 3 V and 5 V
GSM SIM Modules
Narrow Body 4.4 mm 28-Lead TSSOP Package
APPLICATIONS
GSM/DCS/PCS Handsets
TeleMatic Systems
ICO/Iridium Terminals
GENERAL DESCRIPTION
The ADP3404 is a multifunction power management system IC
optimized for GSM cell phones. The wide input voltage range of
3.0 V to 7.0 V makes the ADP3404 ideal for both single cell
Li-Ion and three cell NiMH designs. The current consumption
of the ADP3404 has been optimized for maximum battery life,
featuring a ground current of only 230 µA when the phone is in
standby (digital LDO, analog LDO, and SIM card supply active).
An undervoltage lockout (UVLO) prevents the startup when
there is not enough energy in the battery. All four integrated
LDOs are optimized to power one of the critical sub-blocks of the
phone. Their novel anyCAP® architecture requires only very
small output capacitors for stability, and the LDOs are insensitive
to the capacitors’ equivalent series resistance (ESR). This makes
them stable with any capacitor, including ceramic (MLCC) types
for space-restricted applications.
A step-up converter is implemented to supply both the SIM
module and the level translation circuitry to adapt logic signals
for 3 V and 5 V SIM modules. Sophisticated controls are avail-
able for power-up during battery charging, keypad interface and
charging of an auxiliary back-up capacitor for the real-time clock.
These allow an easy interface between ADP3404, GSM proces-
sor, charger, and keypad. Furthermore, a reset circuit and a
thermal shutdown function have been implemented to support
reliable system design.
FUNCTIONAL BLOCK DIAGRAM
VBAT
ADP3404
DIGITAL
LDO
PWRONKEY
ROWX
PWRONIN
ANALOGON
RESCAP
CHRON
SIMBAT
CAP+
CAP؊
SIMPROG
SIMON
SIMGND
RESETIN
CLKIN
DATAIO
POWER-UP
SEQUENCING
AND
PROTECTION
LOGIC
RTC LDO
XTAL OSC
LDO
ANALOG
LDO
CHARGE
PUMP
LOGIC LEVEL
TRANSLATION
REF
+
BUFFER
I/O CLK RST
VCC
RESET
VRTC
VTCXO
VCCA
VSIM
REFOUT
DGND
AGND
anyCAP is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






ADP3404 Datasheet, Funktion
ADP3404
Table I. LDO Control Logic
Inputs
UVLO CHRON PWRONKEY PWRONIN
LX
HH
HX
HL
HL
HL
X
X
L
H
H
H
X
X
X
L
H
H
X = Don’t care
Bold denotes the active control signal.
ANALOGON
X
X
X
X
L
H
VRTC
Off
On
On
On
On
On
Outputs
VCC VCCA
Off Off
On On
On On
Off Off
On On
On On
REFOUT
Off
On
On
Off
On
On
VTCXO
Off
On
On
Off
Off
On
Table II. VSIM Control Logic
Inputs
VCC RESET SIMON
Off L
On L
On H
On H
On H
X
X
L
H
H
X = Don’t care
SIMPROG
X
X
X
L
H
Outputs
VSIM
Off
Off
Off
3V
5V
VBAT
PWRONKEY
ROWX
ADP3404
20k
UVLO
ADJ
UVLO
OVER
TEMP
PWRONIN
RESCAP
CHRON
ANALOGON
SIMBAT
CAP+
CAP
SIMPROG
SIMON
SIMGND
RESETIN
CLKIN
DATAIO
CHARGER
ON
THRESHOLD
EN
CHARGE
PUMP
3V/5V
EN GND
LOGIC
LEVEL
TRANSLATION
RESET
GENERATOR
DIGITAL LDO
VBAT
VREF
OUT
EN GND PG
POWER GOOD
RTC LDO
VBAT
OUT
EN GND
XTAL OSC LDO
VBAT
VREF
OUT
EN GND
ANALOG LDO
VBAT
VREF
OUT
EN GND
EN
REF
BUFFER
+
1.210V
VCC
2.45V
DGND
VRTC
2.45V
RESET
VTCXO
2.765V
VCCA
2.765V
REFOUT
AGND
I/O CLK RST VSIM
Figure 1. Functional Block Diagram
–6–
REV. 0

6 Page









ADP3404 pdf, datenblatt
ADP3404
Charger Diode Selection
The diode shown in Figure 2 is used to prevent the battery from
discharging into the charger turn-on setting resistors, R1 and R2. A
Schottky diode is recommended to minimize the voltage difference
from the charger to the battery and the power dissipation. Choose
a diode with a current rating high enough to handle both the battery
charging current and the current the ADP3404 will draw if pow-
ered up during charging. The battery charging current is dependent
on the battery chemistry, and the charger circuit. The ADP3404
current will be dependent on the loading.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
1. Split the battery connection to the VBAT and SIMBAT pins
of the ADP3404. Use separate traces for each connection
and locate the input capacitors as close to the pins as possible.
2. SIM input and output capacitors should be returned to the
SIMGND and kept as close as possible to the ADP3404 to
minimize noise. Traces to the SIM charge pump capacitor
should be kept as short as possible to minimize noise.
3. VCCA and VTCXO capacitors should be returned to AGND.
4. VCC and VRTC capacitors should be returned to DGND.
5. Split the ground connections. Use separate traces or planes for
the analog, digital, and power grounds, and tie them together
at a single point, preferably close to the battery return.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline (TSSOP)
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
1
PIN 1
0.006 (0.15)
0.002 (0.05)
15
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
14
0.0433 (1.10)
MAX
SEATING
PLANE
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
8؇
0.0079 (0.20) 0؇
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
–12–
REV. 0

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