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ADP3330 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3330
Beschreibung Low Dropout Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
ADP3330 Datasheet, Funktion
Data Sheet
High Accuracy, Ultralow IQ, 200 mA,
SOT-23, anyCAP Low Dropout Regulator
ADP3330
FEATURES
High accuracy over line and load
±0.7% at +25°C
±1.4% over temperature
Ultralow dropout voltage: 140 mV (typical) at 200 mA
Requires only COUT= 0.47 μF for stability
anyCAP = stable with any type of capacitor, including
multilayer ceramic capacitors (MLCC)
Current and thermal limiting
Low noise
Low shutdown current: <2 µA
2.9 V to 12 V supply range
–40°C to +85°C ambient temperature range
Ultrasmall, thermally enhanced, chip-on-lead™ 6-lead SOT-23
package
APPLICATIONS
Cell phones
Notebook and palmtop computers
Battery-powered systems
PCMCIA regulators
Bar code scanners
Camcorders and cameras
GENERAL DESCRIPTION
The ADP3330 is a member of the Analog Devices, Inc., precision
low dropout (LDO) anyCAP® voltage regulator family of products.
The ADP3330 operates with an input voltage range of 2.9 V to
12 V and delivers a load current up to 200 mA. The ADP3330
stands out from the conventional LDOs with a novel architecture
and an enhanced process that enables it to offer performance
advantages and higher output current than its competition. Its
patented design requires only a minimum output capacitor of
0.47 µF for stability. This device is insensitive to output capacitor
equivalent series resistance (ESR), and is stable with any good
quality capacitor, including ceramic (MLCC) types for space
restricted applications. The ADP3330 achieves exceptional
accuracy of ±0.7% at room temperature and ±1.4% over
temperature, line and load variations. The dropout voltage of
the ADP3330 is only 140 mV (typical) at 200 mA. This device also
includes a safety current limit, thermal overload protection, and
a shutdown feature. In shutdown mode, the ground current is
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
IN 2
ERR 3
THERMAL
PROTECTION
Q1
CC
DRIVER
SD 6
ADP3330
1 OUT
R1
gm
BAND GAP
REF
R2
4
GND
Figure 1.
reduced to less than 2 µA. The ADP3330 has an ultralow
ground current 34 µA (typical) in light load situations.
The 6-lead SOT-23 package has been thermally enhanced using
Analog Devices proprietary chip-on-lead feature to maximize
power dissipation.
VIN
CIN
0.47µF
+
ERR NR
ADP3330
IN OUT
SD GND
VOUT
+ COUT
0.47µF
ON
OFF
Figure 2. Typical Application Circuit
Rev. C
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADP3330 Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Input Supply Voltage
Shutdown Input Voltage
Power Dissipation
Operating Ambient Temperature Range
Operating Junction Temperature Range
θJA (4-Layer Board)
θJA (2-Layer Board)
Storage Temperature Range
Lead Temperature (not a range)
(Soldering 10 seconds)
Vapor Phase (60 seconds)
Infrared (15 seconds)
Rating
−0.3 V to +16 V
−0.3 V to +16 V
Internally limited
−40°C to +85°C
−40°C to +125°C
165°C/W
190°C/W
−65°C to +150°C
300°C
215°C
220°C
ADP3330
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 5 of 16

6 Page









ADP3330 pdf, datenblatt
Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitors
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3330 is stable with
a wide range of capacitor values, types, and ESR (anyCAP). A
capacitor as low as 0.47 µF is all that is needed for stability;
larger capacitors can be used if high output current surges are
anticipated. The ADP3330 is stable with extremely low ESR
capacitors (ESR ≈ 0), such as MLCC or OSCON. Note that the
effective capacitance of some capacitor types may fall less than
the minimum at cold temperature. Ensure that the capacitor
provides more than 0.47 µF at minimum temperature.
Input Bypass Capacitor
An input bypass capacitor is not strictly required, but it is
advisable in any application involving long input wires or high
source impedance. Connecting a 0.47 µF capacitor from IN to
GND reduces the sensitivity of the circuit to printed circuit
board (PCB) layout. If a larger value output capacitor is used, a
larger value input capacitor is also recommended.
NOISE REDUCTION
A noise reduction capacitor (CNR) can be used to further reduce
the noise by 6 dB to 10 dB (see Figure 23). Low leakage
capacitors in the 10 pF to 500 pF range provide the best
performance. Carefully connect to this node to avoid noise
pickup from external sources because the noise reduction pin
(NR) is internally connected to a high impedance node. The
pad connected to this pin must be as small as possible and long
PCB traces are not recommended.
When adding a noise reduction capacitor, use the following
guidelines:
Maintain a minimum load current of 1 mA when not in
shutdown.
For CNR values greater than 500 pF, add a 100 kΩ series
resistor (RNR).
It is important to note that as CNR increases, the turn on time is
delayed. When CNR values are greater than 1 nF, this delay may
be in the order of several milliseconds.
VIN
C1
0.47µF
+
NR
ADP3330-3
IN OUT
ERR
SD GND
CNR
RNR
VOUT = 3.3V
R1
330kΩ
+
C2
0.47µF
Figure 23. Noise Reduction Circuit
ADP3330
CHIP-ON-LEAD PACKAGE
The ADP3330 uses a Chip-on-Lead package design (protected
by U.S. Patent 5929514 A) to ensure the best thermal performance
in the 6-lead SOT-23 footprint. In a standard 6-lead SOT-23
package, the majority of the heat flows out of the ground pin.
The Chip-on-Lead package uses an electrically isolated die
attachment that allows all pins to contribute to the heat
conduction. This technique reduces the thermal resistance to
190°C/W on a 2-layer board as compared to >230°C/W for a
standard SOT-23 lead frame. Figure 24 and Figure 25 show the
difference between the standard 6-lead SOT-23 and the Chip-on-
Lead lead frames.
SILICON
DIE
Figure 24. Normal 6-Lead SOT-23 Package
SILICON DIE WITH
ELECTRICALLY
ISOLATED
DIE ATTACH
Figure 25. Thermally Enhanced, Chip-on-Lead Package
THERMAL OVERLOAD PROTECTION
The ADP3330 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C.
Under extreme conditions, (that is, high ambient temperature
and power dissipation) where die temperature starts to rise
more than 165°C, the output current decreases until the die
temperature has dropped to a safe level. The output current is
restored when the die temperature is reduced.
Current and thermal limit protections protect the device against
accidental overload conditions. For normal operation, device
power dissipation must be externally limited so that the
junction temperatures do not exceed 125°C.
Rev. C | Page 11 of 16

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