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ADP3310AR-28 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3310AR-28
Beschreibung Precision Voltage Regulator Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
ADP3310AR-28 Datasheet, Funktion
a
FEATURES
؎1.5% Accuracy Over Line, Load and Temperature
Low 800 A (Typical) Quiescent Current
Shutdown Current: 1 A (Typical)
Stable with 10 F Load Capacitor
+2.5 V to +15 V Operating Range
Fixed Output Voltage Options: 2.8 V, 3 V, 3.3 V, 5 V
Up to 10 A Output Current
SO-8 Package
–40؇C to +85؇C Ambient Temperature Range
Internal Gate to Source Protective Clamp
Current and Thermal Limiting
Programmable Current Limit
Foldback Current Limit
APPLICATIONS
Desktop Computers
Handheld Instruments
Cellular Telephones
Battery Operated Devices
Solar Powered Instruments
High Efficiency Linear Power Supplies
Battery Chargers
GENERAL DESCRIPTION
The ADP3310 is a precision voltage regulator controller that
can be used with an external Power PMOS device such as the
NDP6020P to form a two chip low dropout linear regulator.
The low quiescent current (800 µA) and the Enable feature
make this device especially suitable for battery powered systems.
The dropout voltage at 1 A is only 70 mV when used with the
NDP6020P, allowing operation with minimal headroom and
prolonging battery useful life. The ADP3310 can drive a wide
range of currents, depending on the external PMOS device used.
Additional features of this device include: high accuracy (± 1.5%)
over line, load and temperature, gate-to-source voltage clamp to
protect the external MOSFET and foldback current limit. A
current limit threshold voltage of 50 mV (typ) allows 50 mof
board metal trace resistance to provide a 1 A current limit.
The ADP3310 operates from a wide input voltage range from
2.5 V to 15 V and is available in a small SO-8 package.
Precision Voltage
Regulator Controller
ADP3310
FUNCTIONAL BLOCK DIAGRAM
ADP3310
EN BIAS
VIN
+
50mV
IS
VREF
GATE
VOUT
GND
VIN
1F
+
RS
50mV
NDP6020P
+
10F
VOUT
ON
OFF
IS GATE
VIN ADP3310 VOUT
EN
GND
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






ADP3310AR-28 Datasheet, Funktion
ADP3310
APPLICATION INFORMATION
The ADP3310 is very easy to use. A P-channel power MOSFET
and a small capacitor on the output is all that is needed to form
an inexpensive ultralow dropout regulator. The advantage of
using the ADP3310 controller is that it can drive a pass PMOS
FET to provide a regulated output at high current.
FET Selection
The type and size of the pass transistor are determined by the
threshold voltage, input-output voltage differential and load
current. The selected PMOS must satisfy the physical and
thermal design requirements. Table I shows a partial list of
manufacturers providing the PMOS devices. To ensure that the
maximum VGS provided by the controller will turn on the FET
at worst case conditions (i.e., temperature and manufacturing
tolerances), the maximum available VGS must be determined.
Maximum VGS is calculated as follows:
(1) VGS = VIN – VBE – IOMAX × RS
IOMAX = Maximum Output Current
RS = Current Sense Resistor
VBE ~ 0.7 V (Room Temp)
~ 0.5 V (Hot)
~ 0.9 V (Cold)
For Example: VIN = 5 V, VO = 3.3 V and IOMAX = 3 A,
VGS = 5 V – 0.7 V – 3 A × 11 m= 4.27 V
Equation (1) applies to a gate-to-source voltage less than the
gate to source clamp voltage.
(2) VDS = VIN – VO
VDS = 5 V – 3.3 V = 1.7 V
If VIN 5 V, logic level FET should be considered.
If VIN > 5 V, either logic level or standard MOSFET can be used.
The difference between VIS and VOUT (VDS) must exceed the
voltage drop due to the load current and the ON resistance of
the FET. As a safety margin, it is recommended to use a MOS-
FET with a VGS at least 1.5 times lower than the calculated VGS
value from Equation 1. Also, in the event the circuit is shorted
to ground, the MOSFET must be able to conduct the maximum
short circuit current. The selected MOSFET must satisfy these
criteria; otherwise, a different pass device should be used. If the
FET data is not available in the catalogue, contact the FET
manufacturer.
Thermal Design
The maximum allowable thermal resistance between the FET
junction and the highest ambient temperature must be taken
into account to determine the type of FET package used. One
square inch of PCB copper area as heatsink yields a typical
θJA ~ 60°C/W for the SOT-223 package and θJA ~ 50°C/W for
the SO-8 package. For substantially lower thermal resistances,
D2PAK or TO-220 type of packages are recommended.
For normal applications, the FET can be directly mounted to the
PCB. But, for higher power applications, an external heat sink is
required to satisfy the θJA requirement and provide adequate heatsink.
Calculating thermal resistance for VIN = 5 V, VO = 3.3 V, and
IO = 3 A:
θ JA
=
T J TAMBMAX
(V DSMAX × IOMAX
)
TJ = Junction Temperature
TAMBMAX = Maximum Ambient Temperature
VDSMAX
IOMAX
θJA
= Maximum Drain to Source Voltage
= Maximum Output Current
=
125 50
1.7 × 3
= 14.7°C/W
For such a low θJA, a P-channel FET from Fairchild, such as
NDP6020P in a heatsink mountable TO-220 package, is
required. The required external heatsink is determined as
follows:
θCA = θJA θJC
θCA = Case-to-Ambient Thermal Resistance
θJA = Junction-to-Ambient Thermal Resistance
θJC = Junction-to-Case Thermal Resistance
θJC = 2°C/W for NDP6020P
θCA = 14.7°C/W – 2°C/W = 12.7°C/W
For a safety margin, select a heatsink with a θCA less than half of
the value calculated above to allow extended duration of short
circuit. In a natural convection environment, a large heatsink
such as 3" length of Type 63020 extrusion from Aavid Engineering
is required.
External Capacitors
The ADP3310 is stable with virtually any good quality capaci-
tors (anyCAP™), independent of the capacitor’s minimum ESR
(Effective Series Resistance) value. The actual value of the ca-
pacitor and its associated ESR depends on the gm and ca-
pacitance of the external PMOS device. A 10 µF capacitor at the
output is sufficient to ensure stability for up to 10 A output
current. Larger capacitors can be used if high output current
surges are anticipated. Extremely low ESR capacitors (ESR0)
such as multilayer ceramic or OSCON are preferred because
they offer lower ripple on the output. For less demanding
requirements, a standard tantalum or even an aluminum
electrolytic is adequate. However, if an aluminum electrolytic is
used, be sure it meets the temperature requirements because
aluminum electrolytic has poor performance over temperature.
Shutdown Mode
Applying a TTL high signal to the EN pin or tying it to the
input pin will enable the output. Pulling this pin low or tying it
to ground will disable the output. In shutdown mode, the
controller’s quiescent current is reduced to less than 1 µA.
Gate-to-Source Clamp
An 8 V gate-to-source voltage clamp is provided to protect the
MOSFET in the event the output is suddenly shorted to
ground. This allows the use of the new, low on-state resistance
(RDSON) FETs.
Short Circuit Protection
The power FET is protected during short circuit conditions
with a foldback type of current limiting which significantly re-
duces the current.
Current Sense Resistor
Current limit is achieved by setting an appropriate current sense
resistor (RS) across the current limit threshold voltage. Current
limit sense resistor RS is calculated as follows:
RS
= 0.05
(1.5 × IO )
anyCAP is a trademark of Analog Devices, Inc.
–6– REV. A

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