PDF ADP3180JRU-REEL7 Data sheet ( Hoja de datos )

Número de pieza	ADP3180JRU-REEL7
Descripción	6-Bit Programmable 2-/ 3-/ 4-Phase Synchronous Buck Controller
Fabricantes	Analog Devices
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No Preview Available ! 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller ADP3180* FEATURES Selectable 2-, 3-, or 4-Phase Operation at up to 1 MHz per Phase ؎14.5 mV Worst-Case Differential Sensing Error over Temperature Logic-Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between All Output Phases Built-In Power Good/Crowbar Blanking Supports On-the-Fly VID Code Changes 6-Bit Digitally Programmable 0.8375 V to 1.6 V Output Programmable Short Circuit Protection with Programmable Latch-Off Delay APPLICATIONS Desktop PC Power Supplies for: Next Generation Intel® Processors VRM Modules GENERAL DESCRIPTION The ADP3180 is a highly efﬁcient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high per- formance Intel processors. It uses an internal 6-bit DAC to read a voltage identiﬁcation (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6 V, and uses a multimode PWM architecture to drive the logic level outputs at a programmable switching frequency that can be optimized for VR size and efﬁciency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four comple- mentary buck switching stages. The ADP3180 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3180 also provides accurate and reliable short circuit protection, adjustable current limiting, and a delayed Power Good output that accommodates on-the-ﬂy output voltage changes requested by the CPU. ADP3180 is speciﬁed over the commercial temperature range of 0°C to 85°C and is available in a 28-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM VCC 28 RAMPADJ RT 14 13 ADP3180 11 EN UVLO SHUTDOWN AND BIAS 19 GND DAC +150mV CSREF DAC –250mV 10 PWRGD DELAY 15 ILIMIT EN 12 DELAY SOFT- START OSCILLATOR CMP SET EN RESET 27 PWM1 CURRENT BALANCING CIRCUIT CMP RESET 26 2-, 3-, 4-PHASE PWM2 DRIVER LOGIC CMP RESET 25 PWM3 CMP RESET CROWBAR CURRENT LIMIT CURRENT LIMIT CIRCUIT 24 PWM4 23 SW1 22 SW2 21 SW3 20 SW4 17 CSSUM 16 CSREF 18 CSCOMP 9 COMP 8 FB PRECISION REFERENCE VID DAC 7 FBRTN 123456 VID4 VID3 VID2 VID1 VID0 VID5 Patent Pending REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or oth- erwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page ADP3180 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1–6 VID4–VID0, Voltage Identiﬁcation DAC Inputs. These six pins are pulled up to an internal reference, providing a logic VID5 one if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3180 going into a “No CPU” mode, shutting off its PWM outputs. 7 FBRTN Feedback Return. VID DAC and error ampliﬁer reference for remote sensing of the output voltage. 8 FB Feedback Input. Error ampliﬁer input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. 9 COMP Error Ampliﬁer Output and Compensation Point 10 PWRGD Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the proper operating range. 11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs. 12 DELAY Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay time. 13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. 14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. 15 ILIMIT Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter.This pin is actively pulled low when the ADP3180 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high side and low side outputs should go low. 16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense ampliﬁer and the Power Good and Crowbar functions. This pin should be connected to the common point of the output inductors. 17 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. 19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. 20–23 SW4–SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 24–27 PWM4– PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND will cause that phase to turn off, allowing the ADP3180 to operate as a 2-, 3-, or 4-phase controller. 28 VCC Supply Voltage for the Device. REV. 0 –5– 5 Page ADP3180 VIN 12V VIN RTN L1 1.6␮H 470␮F/16V ؋ 6 Nichicon PW Series ++ C1 C6 D1 1N4148WS D2 1N4148WS C7 4.7␮F D3 1N4148WS C11 4.7␮F D4 1N4148WS C15 4.7␮F U2 C8 ADP3418 100nF 1 BST DRVH 8 2 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 C9 4.7␮F Q1 IPD12N03L U3 C12 ADP3418 100nF 1 BST DRVH 8 2 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 Q3 IPD06N03L Q2 IPD06N03L C13 4.7␮F Q4 IPD12N03L U4 ADP3418 1 BST DRVH 8 2 IN SW 7 3 OD PGND 6 4 VCC DRVL 5 Q6 IPD06N03L Q5 IPD06N03L C16 100nF C17 4.7␮F Q7 IPD12N03L Q8 IPD06N03L Q9 IPD06N03L L2 600nH/1.6m⍀ C10 4.7nF R1 2.2⍀ 820␮F/2.5V ؋ 8 Fujitsu RE Series 8m⍀ ESR (each) ++ C21 C28 10␮F ؋ 23MLCC AROUND SOCKET L3 600nH/1.6m⍀ C14 4.7nF R2 2.2⍀ L4 600nH/1.6m⍀ C18 4.7nF R3 2.2⍀ RTH 100k⍀, 5% VCC(CORE) 0.8375V–1.6V 65A AVG, 74A PK VCC(CORE) RTN POWER GOOD ENABLE SEE THEORY OF OPERATION SECTION FOR DESCRIPTION OF OPTIONAL RSW RESISTORS REV. 0 R4 C19 + C20 10⍀ 1␮F 33␮F RR U1 383k⍀ ADP3180 1 VID4 VCC 28 2 VID3 PWM1 27 FROM CPU 3 VID2 4 VID1 PWM2 26 PWM3 25 CB 1.5nF RB CA RA 1.33k⍀ 390pF 16.9k⍀ CFB 33pF 5 VID0 6 VID5 7 FBRTN 8 FB 9 COMP 10 PWRGD 11 EN PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 RSW1* RSW2* RSW3* CCS2 RCS1 1.5nF 35.7k⍀ RPH3 124k⍀ RPH1 124k⍀ RCS2 73.2k⍀ RPH2 124k⍀ CDLY 39nF RDLY 390k⍀ RT 249k⍀ 12 DELAY 13 RT CSSUM 17 CCS1 2.2nF CSREF 16 14 RAMPADJ ILIMIT 15 RLIM 200k⍀ Figure 4. 65 A Intel Pentium® 4 CPU Supply Circuit, VRD 10 Design –11– 11 Page

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