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ADP3180JRU-REEL Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3180JRU-REEL
Beschreibung 6-Bit Programmable 2-/ 3-/ 4-Phase Synchronous Buck Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADP3180JRU-REEL Datasheet, Funktion
6-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3180*
FEATURES
Selectable 2-, 3-, or 4-Phase Operation at up to
1 MHz per Phase
؎14.5 mV Worst-Case Differential Sensing Error over
Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
Active Current Balancing between All Output Phases
Built-In Power Good/Crowbar Blanking Supports
On-the-Fly VID Code Changes
6-Bit Digitally Programmable 0.8375 V to 1.6 V Output
Programmable Short Circuit Protection with
Programmable Latch-Off Delay
APPLICATIONS
Desktop PC Power Supplies for:
Next Generation Intel® Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3180 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel processors. It uses an internal 6-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.8375 V and
1.6 V, and uses a multimode PWM architecture to drive the logic
level outputs at a programmable switching frequency that can be
optimized for VR size and efficiency. The phase relationship of the
output signals can be programmed to provide 2-, 3-, or 4-phase
operation, allowing for the construction of up to four comple-
mentary buck switching stages.
The ADP3180 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3180 also provides accurate and reliable short
circuit protection, adjustable current limiting, and a delayed
Power Good output that accommodates on-the-fly output voltage
changes requested by the CPU.
ADP3180 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ RT
14 13
ADP3180
11
EN
UVLO
SHUTDOWN
AND BIAS
19
GND DAC
+150mV
CSREF
DAC
–250mV
10
PWRGD
DELAY
15
ILIMIT
EN
12
DELAY
SOFT-
START
OSCILLATOR
CMP
SET EN
RESET
27
PWM1
CURRENT
BALANCING
CIRCUIT
CMP RESET
26
2-, 3-, 4-PHASE PWM2
DRIVER LOGIC
CMP RESET
25
PWM3
CMP RESET
CROWBAR
CURRENT
LIMIT
CURRENT
LIMIT
CIRCUIT
24
PWM4
23
SW1
22
SW2
21
SW3
20
SW4
17
CSSUM
16
CSREF
18
CSCOMP
9
COMP
8
FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
123456
VID4 VID3 VID2 VID1 VID0 VID5
*Patent Pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.






ADP3180JRU-REEL Datasheet, Funktion
ADP3180–Typical Performance Characteristics
4
3
2
1
0
0 50 100 150 200 250 300
RT VALUE – k
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH
TPC 1. Master Clock Frequency vs. RT
5.3
TA = 25؇C
4-PHASE OPERATION
5.2
5.1
5.0
4.9
4.8
4.7
4.6
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
MASTER CLOCK FREQUENCY – MHz
4.0
TPC 2. Supply Current vs. Master Clock Frequency
TEST CIRCUITS
ADP3180
12V 28 VCC
39k
1k
1.0V
18 CSCOMP
100nF
17 CSSUM
16 CSREF
19 GND
VOS =
CSCOMP – 1V
40
Test Circuit 1. Current Sense Amplifier VOS
ADP3180
12V 28 VCC
10k
200k
V
200k
100nF
1.0V
8 FB
9 COMP
18 CSCOMP
17 CSSUM
16 CSREF
19 GND
VFB = FBV = 80mV – FBV = 0mV
Test Circuit 2. Positioning Voltage
ADP3180
1 VID4
VCC 28
2 VID3
PWM1 27
+
1F
6-BIT CODE
3 VID2
4 VID1
PWM2 26
PWM3 25
5 VID0
PWM4 24
6 VID5
SW1 23
7 FBRTN
SW2 22
8 FB
SW3 21
1k
9 COMP
10 PWRGD
SW4 20
GND 19
1.25V
11 EN
12 DELAY
4.7nF 250k13 RT
CSCOMP 18
CSSUM 17
CSREF 16
20k
14 RAMPADJ
ILIMIT 15
250k
12V
100nF
100nF
Test Circuit 3. Closed-Loop Output Voltage Accuracy
–6– REV. 0

6 Page









ADP3180JRU-REEL pdf, datenblatt
ADP3180
Setting the Clock Frequency
The ADP3180 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 800 kHz sets
the switching frequency of each phase, fSW, to 267 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components. TPC 1 shows that to
achieve an 800 kHz oscillator frequency, the correct value for RT
is 249 kW. Alternatively, the value for RT can be calculated using:
1
( )RT =
n × fSW × 5.83 pF
1.5
1
M
(1)
where 5.83 pF and 1.5 MW are internal IC component values.
For good initial accuracy and frequency stability, it is recom-
mended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay Times
Because the soft-start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft-start ramp. This
ramp is generated with a 20 µA internal current source. The value
of RDLY will have a second order impact on the soft-start time
because it sinks part of the current source to ground. However, as
long as RDLY is kept greater than 200 kW, this effect is minor. The
value for CDLY can be approximated using:
CDLY
=
 20
µA
2
VVID
× RDLY

× tSS
VVID
(2)
where tSS is the desired soft-start time. Assuming an RDLY of
390 kW and a desired a soft-start time of 3 ms, CDLY is 36 nF.
The closest standard value for CDLY is 39 nF. Once CDLY has been
chosen, RDLY can be calculated for the current limit latch-off
time using:
RDLY
= 1.96 × tDELAY
CDLY
(3)
If the result for RDLY is less than 200 kW, a smaller soft-start time
should be considered by recalculating the equation for CDLY, or a
longer latch-off time should be used. In no case should RDLY be
less than 200 kW. In this example, a delay time of 8 ms gives
RDLY = 402 kW. The closest standard 5% value is 390 kW.
Inductor Selection
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple cur-
rent, which increases the output ripple voltage and conduction
losses in the MOSFETs, but allows using smaller inductors and,
for a specified peak-to-peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower ripple
current and reduced conduction losses but requires larger
inductors and more output capacitance for the same peak-to-
peak transient deviation. In any multiphase converter, a practical
value for the peak-to-peak inductor ripple current is less than
50% of the maximum dc current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator fre-
quency, and peak-to-peak ripple current in the inductor.
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage:
( )IR
=
VVID ×
fSW
1D
×L
(4)
( ( ))L
VVID
× RO × 1 n ×
fSW × VRIPPLE
D
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields:
( )1.5 V × 1.3 mΩ × 10.375
L 267 kHz × 10 mV
= 456 nH
If the ripple voltage ends up less than that designed for, the
inductor can be made smaller until the ripple value is met. This
will allow optimal transient response and minimum output
decoupling.
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 600 nH inductor is
a good choice for a starting point and gives a calculated ripple
current of 8.2 A. The inductor should not saturate at the peak
current of 25.8 A and should be able to handle the sum of the
power dissipation caused by the average current of 22.7 A in the
winding and core loss.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR will
cause excessive power losses, while too small a value will lead to
increased measurement error. A good rule of thumb is to have the
DCR be about 1 to 1½ times the droop resistance (RO). For our
example, we are using an inductor with a DCR of 1.6 mW.
Designing an Inductor
Once the inductance and DCR are known, the next step is to
either design an inductor or find a standard inductor that comes
as close as possible to meeting the overall design goals. It is also
important to have the inductance and DCR tolerance specified
to control the accuracy of the system. 15% inductance and 8%
DCR (at room temperature) are reasonable tolerances that most
manufacturers can meet.
The first decision in designing the inductor is to choose the core
material. There are several possibilities for providing low core
loss at high frequencies. Two examples are the powder cores (e.g.,
Kool-Mµ® from Magnetics, Inc. or Micrometals) and the gapped
soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency
powdered iron cores should be avoided due to their high core
loss, especially when the inductor value is relatively low and the
ripple current is high.
The best choice for a core geometry is a closed-loop type, such
as a pot core, PQ, U, and E core, or toroid. A good compromise
between price and performance is a core with a toroidal shape.
There are many useful references for quickly designing a power
inductor, such as:
Magnetics Design References
Magnetic Designer Software
Intusoft (www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
Converters, by William T. McLyman, Kg Magnetics, Inc.
ISBN 1883107008
–12–
REV. 0

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