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ADP3179JRU Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3179JRU
Beschreibung 4-Bit Programmable Synchronous Buck Controllers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADP3179JRU Datasheet, Funktion
a
FEATURES
Optimally Compensated Active Voltage Positioning
with Gain and Offset Adjustment (ADOPT™) for
Superior Load Transient Response
Complies with VRM 8.4 Specifications with Lowest
System Cost
4-Bit Digitally Programmable 1.3 V to 2.05 V Output
N-Channel Synchronous Buck Driver
Two On-Board Linear Regulator Controllers
Total Accuracy ؎0.8% Over Temperature
High Efficiency Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects Micro-
processors with No Additional External Components
APPLICATIONS
Core Supply Voltage Generation for:
Intel Pentium® III
Intel Celeron™
4-Bit Programmable
Synchronous Buck Controllers
ADP3159/ADP3179
FUNCTIONAL BLOCK DIAGRAM
GND
LRFB1
LRDRV1
LRFB2
LRDRV2
COMP
VCC
CT
ADP3159/ADP3179
UVLO
& BIAS
OSCILLATOR
SET
RESET
REFERENCE
CROWBAR
REF
PWM
DRIVE
VLR1
DAC+20%
VLR2
REF
DAC–20%
CMP
–+
gm
VID DAC
DRVH
DRVL
PWRGD
CS–
CS+
FB
GENERAL DESCRIPTION
The ADP3159 and ADP3179 are highly efficient output syn-
chronous buck switching regulator controllers optimized for
converting a 5 V main supply into the core supply voltage
required by high-performance processors. These devices use an
internal 4-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 2.05 V. They use a current mode,
constant off-time architecture to drive two N-channel
MOSFETs at a programmable switching frequency that can be
optimized for regulator size and efficiency.
The ADP3159 and ADP3179 also use a unique supplemental
regulation technique called Analog Devices Optimal Position-
ing Technology (ADOPT) to enhance load transient
performance. Active voltage positioning results in a dc/dc con-
verter that meets the stringent output voltage specifications
for high-performance processors, with the minimum number
VID3 VID2 VID1 VID0
of output capacitors and smallest footprint. Unlike voltage-
mode and standard current-mode architectures, active voltage
positioning adjusts the output voltage as a function of the load
current so it is always optimally positioned for a system tran-
sient. The devices also provide accurate and reliable short
circuit protection and adjustable current limiting. They also
include an integrated overvoltage crowbar function to protect
the microprocessor from destruction in case the core supply
exceeds the nominal programmed voltage by more than 20%.
The ADP3159 and ADP3179 contain two fixed-output volt-
age linear regulator controllers that are designed to drive
external N-channel MOSFETs. The outputs are internally
fixed at 2.5 V and 1.8 V in the ADP3159, while the ADP3179
provides adjustable output, which is set using an external
resistor divider. These linear regulators are used to generate
the auxiliary voltages (AGP, GTL, etc.) required in most moth-
erboard designs, and have been designed to provide a high
bandwidth load-transient response.
The ADP3159 and ADP3179 are specified over the commercial
temperature range of 0°C to 70°C and are available in a 20-lead
TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
Celeron is a trademark of Intel Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






ADP3179JRU Datasheet, Funktion
ADP3159/ADP3179
5V
R1
10k
FROM CPU
POWER
GOOD
C2
3.3V 68pF
R2
10k
C15
1F
Q1
SUB45N03-13L
VLR1
2.5V, 2A
C1 +
100F
D2
MBR052LT1
D3
MBR052LT1
C6 L2
1F 1H
ADP3159/
ADP3179
1 NC U1 GND 20
2 VID0
NC 19
3 VID1
DRVH 18
4 VID2
DRVL 17
5 VID3
VCC 16
6 PWRGD LRFB2 15
7 LRFB1 LRDRV2 14
8 LRDRV1 COMP 13
9 FB
CT 12
10 CS
CS+ 11
NC = NO CONNECT
+ C7
22F
Q4
SUB45N03-13L
L1
1.7H
Q3
SUB75N03-07
+ C8
1000F
+ C9
1000F
R12
4m
1000Fx5
24m(EACH)
+ + ++ +
C17 C18 C19 C20 C21
R8
78.7k
C11
68pF
3.3V
C16
1F
R11
10k
C4
2.7nF
Q2
SUB45N03-13L
R7
10.5k
C3
150pF
R4
220
+ C5
100F
VLR2
1.8V,
2A
C10 R3
1nF 220
5V STANDBY
12V
5V
VCC CORE
1.30V TO
2.05V
15A
Figure 3. 15 A Pentium III Application Circuit
On-board Linear Regulator Controllers
The ADP3159 and ADP3179 include two linear regulator controllers
to provide a low cost solution for generating additional supply rails.
In the ADP3159, these regulators are internally set to 2.5 V (LR1)
and 1.8 V (LR2) with ±2.5% accuracy. The ADP3179 is designed
to allow the outputs to be set externally using a resistor divider.
The output voltage is sensed by the high input impedance LRFB(x)
pin and compared to an internal fixed reference.
The LRDRV(x) pin controls the gate of an external N-channel
MOSFET resulting in a negative feedback loop. The only addi-
tional components required are a capacitor and resistor for
stability. Higher output voltages can be generated by placing
a resistor divider between the linear regulator output and its
respective LRFB pin. The maximum output load current is
determined by the size and thermal impedance of the external
power MOSFET that is placed in series with the supply and
controlled by the ADP3159.
The linear regulator controllers have been designed so that they
remain active even when the switching controller is in UVLO
mode to ensure that the output voltages of the linear regulators
will track the 3.3 V supply as required by Intel design specifica-
tions. By diode ORing the VCC input of the IC to the 5 VSB
and 12 V supplies as shown in Figure 3, the switching output
will be disabled in standby mode, but the linear regulators will
begin conducting once VCC rises above about 1 V. During
start-up the linear outputs will track the 3.3 V supply up until
they reach their respective regulation points, regardless of the
state of the 12 V supply. Once the 12 V supply has exceeded the
5 VSB supply by more than a diode drop, the controller IC
will track the 12 V supply. Once the 12 V supply has risen
above the UVLO value, the switching regulator will begin its
start-up sequence.
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Table I. Output Voltage vs. VID Code
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOUT(NOM)
1.30 V
1.35 V
1.40 V
1.45 V
1.50 V
1.55 V
1.60 V
1.65 V
1.70 V
1.75 V
1.80 V
1.85 V
1.90 V
1.95 V
2.00 V
2.05 V
–6– REV. A

6 Page









ADP3179JRU pdf, datenblatt
ADP3159/ADP3179
Efficiency of the Linear Regulators
The efficiency and corresponding power dissipation of each
of the linear regulators are not determined by the controller
IC. Rather, these are a function of input and output voltage and
load current. Efficiency is approximated by the formula:
η = 100% × VOUT
VIN
(34)
The corresponding power dissipation in the MOSFET, together
with any resistance added in series from input to output, is
given by:
PLDO = (VIN VOUT ) × IOUT
(35)
Minimum power dissipation and maximum efficiency are accom-
plished by choosing the lowest available input voltage that exceeds
the desired output voltage. However, if the chosen input source
is itself generated by a linear regulator, its power dissipation will
be increased in proportion to the additional current it must
now provide.
Implementing Current Limit for the Linear Regulators
The circuit of Figure 6 gives an example of a current limit pro-
tection circuit that can be used in conjunction with the linear
regulators. The output voltage is internally set by the LRFB pin.
The value of the current sense resistor may be calculated as
follows:
RS
540 mV
IO( MAX )
= 540 mV
2.2 A
= 250 m
(36)
The power rating of the current sense resistor must be at least:
PD(RS )
=
RS
×
IO
(
MAX
2
)
= 1.2W
(37)
The maximum linear regulator MOSFET junction temperature
with a shorted output is:
TJ( MAX ) = TA + (θ JC × VIN × IO( MAX ) )
TJ( MAX ) = 50°C + (1.4°C/W × (3.3V × 2.2 A) = 60°C (38)
which is within the maximum allowed by the MOSFETs data
sheet specification. The maximum MOSFET junction tempera-
ture at nominal output is:
TJ(NOM ) = TA + (θ JC × (VIN VOUT ) × IO(NOM ) )
TJ(NOM) = 50°C + (1.4°C/W × (3.3V 2.5 V ) × 2 A) = 52°C (39)
This example assumes an infinite heatsink. The practical limita-
tion will be based on the actual heatsink used.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system:
General Recommendations
1. For best results, a four-layer PCB is recommended. This
should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths.
2. Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance introduced
by these current paths is minimized and the via current
rating is not exceeded.
3. If critical signal lines (including the voltage and current
sense lines of the controller IC) must cross through
power circuitry, it is best if a ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the cost of making signal
ground a bit noisier.
4. The GND pin of the controller IC should connect first to
a ceramic bypass capacitor (on the VCC pin) and then into
the power ground plane. However, the ground plane should
not extend under other signal components, including the
ADP3159 itself.
5. The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the
power (e.g., a microprocessor core). If the load is distributed,
the capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
6. Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
7. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise-related operational prob-
lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs, and the power Schottky
diode, if used, including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high-
energy ringing, and it accommodates the high current demand
with minimal voltage loss.
–12–
REV. A

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