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ADP3162 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3162
Beschreibung 5-Bit Programmable 2-Phase Synchronous Buck Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADP3162 Datasheet, Funktion
a
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 8.5 with Lowest System Cost
Active Current Balancing Between Both Output Phases
5-Bit Digitally Programmable 1.05 V to 1.825 V Output
Dual Logic-Level PWM Outputs for Interface to
External High-Power Drivers
Total Output Accuracy ؎0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Tualatin Processors
VRM Modules
5-Bit Programmable 2-Phase
Synchronous Buck Controller
ADP3162
FUNCTIONAL BLOCK DIAGRAM
VCC
REF
GND
CT
COMP
UVLO
& BIAS
3.0V
REFERENCE
SET
RESET
CROWBAR
2-PHASE
DRIVER
LOGIC
CMP3
DAC+24%
OSCILLATOR
ADP3162
CMP
CMP2
DAC–18%
CMP
CMP1
VID
DAC
gm
PWM1
PWM2
PWRGD
CS–
CS+
FB
GENERAL DESCRIPTION
The ADP3162 is a highly efficient dual output synchronous
buck switching regulator controller optimized for converting a
5 V or 12 V main supply into the core supply voltage required by
high-performance processors such as Tualatin. The ADP3162
uses an internal 5-bit DAC to read a voltage identification (VID)
code directly from the processor, which is used to set the output
voltage between 1.05 V and 1.825 V. The ADP3162 uses a
current mode PWM architecture to drive two logic-level outputs
at a programmable switching frequency that can be optimized
for VRM size and efficiency. The output signals are 180 degrees
out of phase, allowing for the construction of two complementary
buck switching stages. These two stages share the dc output
current to reduce overall output voltage ripple. An active cur-
rent balancing function ensures that both phases carry equal
portions of the total load current, even under large transient
loads, to minimize the size of the inductors.
VID3 VID2 VID1 VID0 VID25
The ADP3162 also uses a unique supplemental regulation tech-
nique called active voltage positioning to enhance load transient
performance. Active voltage positioning results in a dc/dc converter
that meets the stringent output voltage specifications for high
performance processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient. The
ADP3162 also provides accurate and reliable short circuit pro-
tection and adjustable current limiting.
The ADP3162 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 16-lead narrow body
SOIC package.
ADOPT is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






ADP3162 Datasheet, Funktion
ADP3162
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator are the
main control elements. The voltage at the CT pin of the oscilla-
tor ramps between 0 V and 3 V. When that voltage reaches 3 V,
the oscillator sets the driver logic, which sets PWM1 high. Dur-
ing the ON time of Phase 1, the driver IC turns on the high-side
MOSFET. The CS+ and CS– pins monitor the current through
the sense resistor that feeds both high-side MOSFETs. When
the voltage between the two pins exceeds the threshold level
set by the voltage error amplifier (gm), the driver logic is reset
and the PWM output goes low. This signals the driver IC to turn
off the high-side MOSFET and turn on the low-side MOSFET.
On the next cycle of the oscillator, the driver logic toggles and
sets PWM2 high. On each following cycle of the oscillator, the
outputs toggle between PWM1 and PWM2. In each case, the
current comparator resets the PWM output low when the current
comparator threshold is reached. As the load current increases,
the output voltage starts to decrease. This causes an increase in
the output of the gm amplifier, which in turn leads to an increase
in the current comparator threshold, thus programming more
current to be delivered to the output so that voltage regulation is
maintained.
Active Current Sharing
The ADP3162 ensures current balance in the two phases by
actively sensing the current through a single sense resistor. During
one phase’s ON time, the current through the respective high-side
MOSFET and inductor is measured through the sense resistor
(R4 in Figure 2). When the comparator (CMP1 in the Functional
Block Diagram) threshold programmed by the gm amplifier is
reached, the high-side MOSFET turns off. In the next cycle the
ADP3162 switches to the second phase. The current is measured
with the same sense resistor and the same internal comparator,
ensuring accurate matching. This scheme is immune to imbalances
in the MOSFETs’ RDS(ON) and inductors’ parasitic resistances.
If for some reason one of the phases fails, the other phase will still
be limited to its maximum output current (one-half of the short
circuit current limit). If this is not sufficient to supply the load,
the output voltage will droop and cause the PWRGD output to
signal that the output voltage has fallen out of its specified range.
Short Circuit Protection
The ADP3162 has multiple levels of short circuit protection to
ensure fail-safe operation. The sense resistor and the maximum
current sense threshold voltage given in the specifications set the
peak current limit.
When the load current exceeds the current limit, the excess current
discharges the output capacitor. When the output voltage is below
the foldback threshold VFB(LOW), the maximum deliverable output
current is cut by reducing the current sense threshold from the
current limit threshold, VCS(CL), to the foldback threshold,
VCS(FOLD). Along with the resulting current foldback, the oscilla-
tor frequency is reduced by a factor of five when the output is
0 V. This further reduces the average current in short circuit.
Power-Good Monitoring
The Power-Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the specified range of
the nominal output voltage requested by the VID DAC. PWRGD
will go low if the output is outside this range.
Output Crowbar
The ADP3162 includes a crowbar comparator that senses when
the output voltage rises higher than the specified trip thresh-
old, VCROWBAR. This comparator overrides the control loop and
sets both PWM outputs low. The driver ICs turn off the high side
MOSFETs and turn on the low-side MOSFETs, thus pulling the
output down as the reversed current builds up in the inductors. If
the output overvoltage is due to a short of the high side MOSFET,
this action will current limit the input supply or blow its fuse,
VIN 5V
VIN RTN
12V VCC
+
C12
+ ++
C13 C14 C15
1000F ؋ 4
R6
10
RA
10.1k
1%
FROM
CPU
RB
19.1k
1%
COC
3.3nF
U1
ADP3162
1 VID3
VCC 16
2 VID2
REF 15
3 VID1
CS14
4 VID0 PWM1 13
5 VID25 PWM2 12
6 COMP CS+ 11
7 FB PWRGD 10
8 CT
GND 9
C1
91pF
C4
4.7F
C22 1nF
R7
20
C21
15nF
R8
330
C23
330pF
C26
4.7F
R5
2.4k
Z1
ZMM5236BCT
D1
MBR052LTI
Q5
FMMT18
1
R4
4m
C9
1F
U2
ADP3412
BST DRVH 8
2 IN
SW 7
3 DLY PGND 6
C5 C7
1F 15pF
4 VCC DRVL 5
Q1
IRL3803
L1
1H
Q2
IRL3803
D2
MBR052LTI
C10
1F
U3
ADP3412
1 BST DRVH 8
2 IN
SW 7
Q3
IRL3803
L2
1H
1000F ؋ 8
RUBYCON ZA SERIES
24mESR (EACH)
C2
100pF
R1
1k
C6 C8
1F 15pF
3 DLY PGND 6
4 VCC DRVL 5
Q4
IRL3803
C16 C17 C18 C19 C20 C27 C28 C29
VCC(CORE)
1.7V
30A
VCC(CORE)RTN
Figure 2. 23 A Pentium® III CPU Supply Circuit
Pentium is a registered trademark of Intel Corporation.
–6–
REV. A

6 Page









ADP3162 pdf, datenblatt
ADP3162
Signal Circuitry
15. The output voltage is sensed and regulated between the FB
pin and the GND pin (which connects to the signal ground
plane). The output current is sensed (as a voltage) by the
CS+ and CS– pins. In order to avoid differential mode
noise pickup in the sensed signal, the loop area should be
small. Thus the FB trace should be routed atop the signal
ground plane, and the CS+ and CS– pins should be routed
as a closely coupled pair (the CS+ pin should be over the
signal ground plane as well).
16. The CS+ and CS– traces should be Kelvin-connected to
the current sense resistor so that the additional voltage drop
due to current flow on the PCB at the current sense resistor
connections does not affect the sensed voltage.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC
(R-16A/SO-16)
0.3937 (10.00)
0.3859 (9.80)
0.1574 (4.00) 16
0.1497 (3.80)
1
9 0.2440 (6.20)
0.2284 (5.80)
8
PIN 1 0.050 (1.27) 0.0688 (1.75)
BSC
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)؋ 45؇
0.0098 (0.25)
0.0040 (0.10)
8؇
0.0192 (0.49) SEATING
0.0138 (0.35) PLANE
0.0099 (0.25) 0؇
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Change to Output Voltage and Output Current Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to APPLICATION INFORMATION section, including equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
–12–
REV. A

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