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ADP3156 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3156
Beschreibung Dual Power Supply Controller for Desktop Systems
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADP3156 Datasheet, Funktion
a
Dual Power Supply Controller
for Desktop Systems
ADP3156
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
Fixed 1.5 V, 1.8 V and 2.5 V Output Versions
Dual N-Channel Synchronous Driver
On-Board Linear Regulator Controller
Total Output Accuracy ؎1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Loads with
No Additional External Components
Power Good Output
SO-16 Package
APPLICATIONS
Desktop Computer Supplies
ACPI-Compliant Power Systems
General Purpose DC-DC Converters
GENERAL DESCRIPTION
The ADP3156 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 3.3 V or 5 V
main supply into lower supply voltages required on the mother-
boards of Pentium® III and other high performance processor
systems. The ADP3156 uses a current mode, constant off-time
architecture to drive two external N-channel MOSFETs at a
programmable switching frequency that can be optimized for
size and efficiency. It also uses a unique supplemental regulation
technique called active voltage positioning to enhance load
transient performance. Active voltage positioning results in a
DC/DC converter that provides the best possible transient re-
sponse using the minimum number of output capacitors and
smallest footprint. Unlike voltage-mode and standard current-
mode architectures, active voltage positioning adjusts the output
voltage as a function of the load current so that it is always
optimally positioned for a system transient.
The ADP3156 provides accurate and reliable short circuit
protection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
DELAY
NONOVERLAP
SD
DRIVE
VREF +15%
CROWBAR
IN OFF
CMPI
VREF +5% VREF –5%
2R
S
Q
R
VT2
VT1
VREF
gm
R
REFERENCE
CT CMPT
OFF-TIME VIN
CONTROL SENSE–
1.20V
ADP3156
VLDO
FB
CMP
The ADP3156 contains a linear regulator controller that is
designed to drive an external N-channel MOSFET. This linear
regulator is used to generate the auxiliary voltages (AGP, GTL,
etc.) required in most motherboard designs, and has been de-
signed to provide a high bandwidth load-transient response. A
pair of external feedback resistors sets the linear regulator out-
put voltage.
VO2
1000F
VCC +12V
22F 1F
R1
35k
20k
R2
SD VCC
DRIVE1
VLDO
ADP3156
CCOMP
200pF
SENSE+
FB
CMP SENSE–
DRIVE2
CT
AGND PGND
VIN +5V
CIN
+
L RSENSE
VO
+
1nF CO
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






ADP3156 Datasheet, Funktion
ADP3156
1k
4700pF
12V
SD ADP3156 VCC
CMP
DRIVE1
DRIVE2
CT SENSE+
SENSE–
AGND PGND
1F 0.1F
VOUT
1.2V
100k
OP27
0.1F
Figure 12. Closed-Loop Test Circuit for Accuracy
THEORY OF OPERATION
The ADP3156 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in a
synchronous buck topology. Constant off-time operation offers
several performance advantages, including that no slope com-
pensation is required for stable operation. A unique feature of
the constant-off-time control technique is that since the off-time
is fixed, the converter’s switching frequency is a function of the
ratio of input voltage to output voltage. The fixed off-time is
programmed by the value of an external capacitor connected to
the CT pin. The on-time varies in such a way that a regulated
output voltage is maintained as described below in the cycle-by-
cycle operation. Under fixed operating conditions the on-time
does not vary, and it varies only slightly as a function of load.
This means that switching frequency is fairly constant in stan-
dard VRM applications. In order to maintain a ripple current in
the inductor, which is independent of the output voltage (which
also helps control losses and simplify the inductor design), the
off-time is made proportional to the value of the output voltage.
Normally, the output voltage is constant and therefore the off-
time is constant as well.
Active Voltage Positioning
The output voltage is sensed at the SENSE– pin. SENSE– is
connected to an internal voltage divider. The output of the
divider is then compared to the internal reference. A unique
supplemental regulation technique called active voltage posi-
tioning with optimal compensation adjusts the output voltage as
a function of the load current so that it is always optimally posi-
tioned for a load transient. Standard (passive) voltage position-
ing, sometimes recommended for use with other architectures,
has poor dynamic performance which renders it ineffective
under the stringent repetitive transient conditions specified in
Intel VRM documents. Consequently, such techniques do not
allow the minimum possible number of output capacitors to be
used. Optimally compensated active voltage positioning, as used
in the ADP3156, provides a bandwidth for transient response
that is limited only by parasitic output inductance. This yields
an optimal load transient response with the minimum number
of output capacitors.
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator (CMPI)
are the main control elements. (See the block diagram of Figure
3). During the on-time of the high side MOSFET, CMPI
monitors the voltage between the SENSE+ and SENSE– pins.
When the voltage level between the two pins reaches the thresh-
old level VT1, the high side drive output is switched to ground,
which turns off the high side MOSFET. The timing capacitor
CT is then discharged at a rate determined by the off-time con-
troller. While the timing capacitor is discharging, the low side
drive output goes high, turning on the low side MOSFET. When
the voltage level on the timing capacitor has discharged to the
threshold voltage level VT2, comparator CMPT resets the SR
flip-flop. The output of the flip-flop forces the low side drive
output to go low and the high side drive output to go high. As a
result, the low side switch is turned off and the high side switch
is turned on. The sequence is then repeated. As the load current
increases, the output voltage starts to decrease. This causes an
increase in the output of the voltage-error amplifier, which, in
turn, leads to an increase in the current comparator threshold
VT1, thus tracking the load current. To prevent cross conduc-
tion of the external MOSFETs, feedback is incorporated to
sense the state of the driver output pins. Before the low side
drive output can go high, the high side drive output must be
low. Likewise, the high side drive output is unable to go high
while the low side drive output is high.
Power Good
The ADP3156 has an internal monitor that senses the output
voltage and drives the PWRGD pin of the device. This pin is an
open drain output whose high level (when connected to a pull-
up resistor) indicates that the output voltage has been within a
± 5% regulation band of the targeted value for more than 500 µs.
The PWRGD pin will go low if the output is outside the regula-
tion band for more than 500 µs.
Output Crowbar
An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 15% greater than the
targeted value, the ADP3156 will turn on the lower MOSFET,
which will current-limit the source power supply or blow its
fuse, pull down the output voltage, and thus save the micropro-
cessor from destruction. The crowbar function releases at ap-
proximately 50% of the nominal output voltage. For example, if
the output is programmed to 2.0 V, but is pulled up to 2.3 V or
above, the crowbar will turn on the lower MOSFET. If in this
case the output is pulled down to less than 1.0 V, the crowbar
will release, allowing the output voltage to recover to 2.0 V if
the fault condition has been removed.
Shutdown
The ADP3156 has a shutdown (SD) pin that is pulled down by
an internal resistor. In this condition the device functions nor-
mally. This pin should be pulled high to disable the output
drives.
APPLICATION INFORMATION
A number of power conversion requirements must be consid-
ered when designing an ACPI compliant system. In normal
operating mode, 12 V, 5 V and 3.3 V are available from the
main supply. These voltages need to be converted into the
appropriate supply voltages for the Northbridge core, the
Southbridge core and RAMBUS memory, as well as supplies for
GTL and I/O drivers, CMOS memory and clock and graphics
(AGP) circuits.
–6– REV. 0

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ADP3156 pdf, datenblatt
ADP3156
9. Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
10. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise-related operational prob-
lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs, and the power Schottky
diode if used, including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high-
energy ringing, and it accommodates the high current de-
mand with minimal voltage loss.
11. A power Schottky diode (1~2 Adc rating) placed from the
lower FET’s source (anode) to drain (cathode) will help to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET turn-
ing on (necessary to prevent cross-conduction). The circu-
lating current in the power converter, no longer finding a
path for current through the channel of the lower FET,
draws current through the inherent body-drain diode of the
FET. The upper FET turns on, and the reverse recovery
characteristic of the lower FET’s body-drain diode prevents
the drain voltage from being pulled high quickly. The upper
FET then conducts very large current while it momentarily
has a high voltage forced across it, which translates into
added power dissipation in the upper FET. The Schottky
diode minimizes this problem by carrying a majority of the
circulating current when the lower FET is turned off, and by
virtue of its essentially nonexistent reverse recovery time.
12. A small ferrite bead inductor placed in series with the drain
of the lower FET can also help to reduce this previously
described source of switching power loss.
13. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias both
directly on the mounting pad and immediately surrounding
it is recommended. Two important reasons for this are:
improved current rating through the vias (if it is a current
path), and improved thermal performance—especially if the
vias extended to the opposite side of the PCB where a plane
can more readily transfer the heat to the air.
14. The output power path, though not as critical as the switch-
ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out-
put capacitors, and back to the input capacitors.
15. For best EMI containment, the power ground plane should
extend fully under all the power components except the
output capacitors. These are: the input capacitors, the power
MOSFETs and Schottky diode, the inductor, the current
sense resistor, and any snubbing elements that might be
added to dampen ringing. Avoid extending the power ground
under any other circuitry or signal lines, including the volt-
age and current sense lines.
Signal Circuitry
16. The output voltage is sensed and regulated between the
AGND pin (which connects to the signal ground plane) and
the SENSE– pin. The output current is sensed (as a voltage)
and regulated between the SENSE– pin and the SENSE+
pin. In order to avoid differential mode noise pickup in
those sensed signals, their loop areas should be small. Thus
the SENSE– trace should be routed atop the signal ground
plane, and the SENSE+ and SENSE– traces should be routed
as a closely coupled pair (SENSE+ should be over the signal
ground plane as well).
17. The SENSE+ and SENSE– traces should be Kelvin con-
nected to the current sense resistor so that the additional
voltage drop due to current flow on the PCB at the current
sense resistor connections does not affect the sensed voltage.
It is desirable to both have the ADP3156 close to the output
capacitor bank and not in the output power path so that any
voltage drop between the output capacitors and the AGND
pin is minimized, and voltage regulation is not compromised.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Standard Small Outline Package (SOIC)
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
0.1574 (4.00) 16
0.1497 (3.80)
1
9 0.2440 (6.20)
0.2284 (5.80)
8
PIN 1 0.050 (1.27) 0.0688 (1.75)
BSC
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)؋ 45؇
0.0098 (0.25)
0.0040 (0.10)
8؇
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0099 (0.25)
0.0075 (0.19)
0؇
0.0500 (1.27)
0.0160 (0.41)
–12–
REV. 0

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