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PDF ADP3155 Data sheet ( Hoja de datos )
| Número de pieza | ADP3155 | |
| Descripción | 5-Bit Programmable Triple Power Supply Controller for Pentium III Processors | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a 5-Bit Programmable Triple Power Supply
Controller for Pentium® III Processors
ADP3155
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
VRM 8.2, VRM 8.3 and VRM 8.4-Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Two Onboard Linear Regulator Controllers
Total Output Accuracy ؎1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Micro-
processors, with No Additional External Components
Power Good Output
TSSOP-20 Package
APPLICATIONS
Desktop PC Power Supplies for:
Pentium II and Pentium III Processor Families
AMD-K6 Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3155 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup-
ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3155 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3155 uses a current-
mode, constant off-time architecture to drive two external N-
channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position-
ing to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and the smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient.
The ADP3155 provides accurate and reliable short circuit pro-
tection and adjustable current limiting. It also includes an inte-
grated overvoltage crowbar function to protect the microprocessor
from destruction in case the core supply exceeds the nominal
programmed voltage by more than 15%.
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE–
SD
CT
CMP
NONOVERLAP
DRIVE
VREF
+15%
DELAY
CROWBAR
IN OFF
CMPI
S
Q
R
VT2
VREF
+5%
VT1
VREF
–5%
VREF
gm
2R
R
CMPT
OFF-TIME VIN
CONTROL SENSE–
REFERENCE
VLDO2
FB2
ADP3155
DAC
1.20V
VLDO1
FB1
VID4 VID3 VID2 VID1 VID0
The ADP3155 contains two linear regulator controllers that are
designed to drive external N-channel MOSFETs. These linear
regulators are used to generate the auxiliary voltages (AGP,
GTL, etc.) required in most motherboard designs, and have
been designed to provide a high bandwidth load-transient re-
sponse. A pair of external feedback resistors sets each linear
regulator output voltage.
VCC +12V
VIN +5V
R1
22F 1F
SD VCC
CIN
+
DRIVE1
Q1
CCMMPP
R2
CCOMP VINLDO1
ADP3155
L RSENSE
QLDO1
VOLDO1
1F
VINLDO2
R3
R4
20k⍀
SENSE+
VLDO1
SENSE–
FB1
DRIVE2
1nF
Q2
QLDO2
VOLDO2
1F
R5
R6
20k⍀
PGND
VLDO2
150pF
FB2 CT
AGND
VID0–VID4
VO
1.3V TO
+ 3.5V
CO
5-BIT CODE
Figure 1. Typical Application
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
100
95
VOUT = 3.5V
VOUT = 2.8V
90
85 VOUT = 2.0V
80 VOUT = 1.3V
75
70
SEE FIGURE 2
65
1.4 2.8 4.2 5.6 7 8.4 9.8 11.2 12.6 14
OUTPUT CURRENT – Amps
Figure 4. Efficiency vs. Output
Current
Typical Performance Characteristics–ADP3155
450
400
350
300
250
200
150
100
50
0
50 100 200 300 400 500 600 700 800
TIMING CAPACITOR – pF
Figure 5. Frequency vs. Timing
Capacitor
45
40
35
30
25
QGATE(TOTAL) = 100nC
20
15
10
5
0
45 58 83 134 397
OPERATING FREQUENCY – kHz
Figure 6. Supply Current vs.
Operating Frequency
SEE FIGURE 2
IOUT = 10A
PRIMARY
N-DRIVE
DRIVER OUTPUT
1
SECONDARY
N-DRIVE
DRIVER OUTPUT
2
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
Figure 7. Gate Switching Waveforms
SEE FIGURE 2
VCC = +12V
VIN = +5V
IOUT = 10A
100ns/DIV
Figure 8. Driver Transition
Waveforms
OUTPUT VOLTAGE
20mV/DIV
OUTPUT CURRENT
1A TO 19A
10s/DIV
Figure 10. Transient Response,
1 A–19 A of Figure 2 Circuit
VCC VOLTAGE
5V/DIV
3
REGULATOR
OUTPUT VOLTAGE
1V/DIV
4
10ms/DIV
Figure 11. Power-On Start-Up
Waveform
OUTPUT VOLTAGE
20mV/DIV
OUTPUT CURRENT
19A TO 1A
10s/DIV
Figure 9. Transient Response,
19 A–1 A of Figure 2 Circuit
25
TA = +25؇C
SEE FIGURE 13
20
15
10
5
0
OUTPUT ACCURACY – %
Figure 12. Output Accuracy
Distribution, VOUT = 2.0 V
REV. A
–5–
5 Page 
ADP3155
dc biasing, it is simplest to use two resistors to terminate the gm
amplifier output, with the lower resistor tied to ground and the
upper resistor to the 12 V supply of the IC. The values of these
resistors can be calculated using:
and:
RUPPER
=
RC
×VDIV
VOS
RLOWER = RC ×
VOS
VDIV – VOS
where VDIV is the resistor divider supply voltage (e.g., the rec-
ommended 12 V), and VOS is the offset voltage required on the
amplifier to produce the desired offset at the output. VOS is
calculated using Equation 2, where VOUT(OS) is the offset from
the nominal VID-programmed value to the center of the speci-
fied regulation window for the output voltage. (Note this may be
either positive or negative.) For clarification, that offset is given
by:
VOUT(OS)
=
1
2 (VHI
+VLO
)
–VID
where VHI and VLO are the respective upper and lower limits
allowed for regulation.
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
CCOMP
=
CO × ESR
RtTOTAL
Trade-Offs Between DC Load Regulation and AC Load
Regulation
Casual observation of the circuit operation—e.g., with a voltmeter
—would make it appear that the dc load regulation appears
to be rather poor compared to a conventional regulator. This
would be especially noticeable under very light or very heavy
loads where the voltage is “positioned” near one of the extremes
of the regulation window rather than near the nominal center
value. It must be noted and understood that this low gain char-
acteristic (i.e., loose dc load regulation) is inherently required to
allow improved transient containment (i.e., to achieve tighter ac
load regulation). That is, the dc load regulation is intentionally
sacrificed (but kept within specification) in order to minimize
the number of capacitors required to contain the load transients
produced by the CPU.
Linear Regulators
The two ADP3155 linear regulators provide a low cost, conve-
nient and versatile solution for generating additional lower sup-
ply rails that can be programmed in the range 1.2 V–5 V. The
maximum output load current is determined by the size and
thermal impedance of the external N-channel power MOSFET
that is placed in series with the supply and controlled by the
ADP3155. The output voltage, VOLDO1, 2 in Figure 14, is sensed
at the FB pin of the ADP3155 and compared to an internal
1.2 V reference in a negative feedback loop which keeps the
output voltage in regulation. If the load is being reduced or
increased, the FET drive will also be reduced or increased by the
ADP3155 to provide a well regulated ± 1% accurate output
voltage. The output voltage is programmed by adjusting the
value of the external resistor RPROG, shown in Figure 15.
Efficiency of the Linear Regulators
The efficiency and corresponding power dissipation of each of
the linear regulators are not determined by the ADP3155.
Rather, these are a function of input and output voltage and
load current. Efficiency is approximated by the formula:
η = 100% × (VOUT Ϭ VIN)
The corresponding power dissipation in the MOSFET, together
with any resistance added in series from input to output is given
by:
PLDO = (VIN(LDO) – VOUT(LDO)) × IOUT(LDO)
Minimum power dissipation and maximum efficiency are ac-
complished by choosing the lowest available input voltage that
exceeds the desired output voltage. However, if the chosen
input source is itself generated by a linear regulator, its power
dissipation will be increased in proportion to the additional
current it must now provide. For most PC systems, the lowest
available input source for the linear regulators, which is not
itself generated by a linear regulator, is 3.3 V from the main
power supply.
Assuming that the 3.3 V supply is used to provide input power
for a 1.5 V linear regulator output, the efficiency will inherently
be 1.5 V Ϭ 3.3 V, which is less than 50%. The total current
demand in all of the low voltage power rails (e.g., 1.5 V, 1.8 V
and 2.5 V) can produce unacceptable dissipation and junction
temperatures in the linear regulators. For such systems, Analog
Devices recommends the ADP3156—a switching regulator that
generates one of the lower voltage outputs (e.g., 1.8 V), which can
also be used as a power source to the lower voltage outputs
(e.g., 1.5 V). This results is a highly efficient and reliable power
conversion system that can readily handle the combined loading
specifications for the lower system voltages, with room to spare
for the higher current demands and lower voltages of next gen-
eration PC systems.
Features
• Tight DC Regulation Due to 1% Reference and High Gain
• Output Voltage Stays Within Specified Limits at Load
Current Step with 30 A/µs Slope
• Fast Response to Input Voltage or Load Current Transients
Overcurrent protection may be provided by the addition of an
external NPN transistor and an external resistor RS2. The design
specification and procedure is given below.
VOS
=
RC
RtTOTAL
×
0.8 V
+ VOUT(OS)1R.3tT6OTkAΩL
– 1.7 V
RtTOTAL
275 kΩ
+6
RCSIOMAX
(2)
REV. A
–11–
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADP3155.PDF ] | |
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