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PDF ADP1147 Data sheet ( Hoja de datos )
| Número de pieza | ADP1147 | |
| Descripción | High Efficiency Step-Down Switching Regulator Controllers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
High Efficiency Step-Down
Switching Regulator Controllers
ADP1147-3.3/ADP1147-5
FEATURES
Greater Than 95% Efficiency
Current Mode Switching Architecture Provides
Superior Load and Line Transient Response
Wide Input Voltage Range 3.5 V* to 16 V
User Defined Current Limit
Short Circuit Protection
Shutdown Pin
Low Dropout Voltage
Low Standby Current 160 A typ
Low Cost
Available in 8-Lead PDIP or 8-Lead SOIC
APPLICATIONS
Portable Computers
Modems
Cellular Telephones
Portable Equipment
GPS Systems
Handheld Instruments
GENERAL DESCRIPTION
The ADP1147 is part of a family of High Efficiency Step-Down
Switching Regulators. These regulators offer superior load and
line transient response, a user defined current limit and an
automatic power savings mode. The automatic power savings
mode is used to maintain efficiency at lower output currents.
The ADP1147 incorporates a constant off-time, current mode
switching architecture to drive an external P-channel MOSFET
at frequencies up to 250 kHz. Constant off-time switching gen-
erates a constant ripple current in the external inductor. This
results in a wider input voltage operating range of 3.5 V* to
16 V, and a less complex circuit design.
*3.5 volt operation is for the ADP1147-3.3.
VIN (5.2V TO 12V)
+
1F
+ CIN
100F
P-CHANNEL
IRF7204
L*
50H
D1
30BQ040
RSENSE**
0.05⍀
VOUT
5V/2A
+ COUT
390F
0V = NORMAL
1.5V = SHUTDOWN
VIN
P-DRIVE
CC RC
3300pF 1k⍀
ADP1147
SHUTDOWN
ITH SENSE(+)
CT SENSE(–)
CT GND
470pF
1000pF
*COILTRONICS CTX 50–2MP
**KRL SL-1-C1-0R050J
SHUTDOWN
Figure 1. High Efficiency Step-Down Converter
(Typical Application)
FUNCTIONAL BLOCK DIAGRAM
VIN P-DRIVE GROUND SENSE(+) SENSE(–)
ADP1147
SLEEP
S VTH2
VTH1
1
QR
S
T
2
R
QS
V
B
C 10mV to 150mV
13k⍀
G
VOS
1.25V
5pF
100k⍀
OFF-TIME VIN
CONTROL SENSE(–)
REFERENCE
CT ITH SHUTDOWN
A very low dropout voltage with excellent output regulation can
be obtained by minimizing the dc resistance of the Inductor, the
RSENSE resistor, and the RDS(ON) of the P-MOSFET. The power
savings mode conserves power by reducing switching losses at
lower output currents. When the output load current falls below
the minimum required for the continuous mode the ADP1147
will automatically switch to the power savings mode. It will remain
in this mode until the inductor requires additional current or the
sleep mode is entered. In sleep mode with no load the standby
power consumption of the device is reduced to 2.0 mW typical
at VIN = 10 V.
For designs requiring even greater efficiencies refer to the
ADP1148 data sheet.
100
95 VIN = 6 VOLTS
90
VIN = 10 VOLTS
85
80
75
70
65
60
1 10 100 1k 10k
LOAD CURRENT – mA
Figure 2. ADP1147-5 Typical Efficiency, Figure 1 Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
1.8
0°C
1.6
1.4
+25°C
1.2
1.0
0.8 +70°C
0.6
0.4
0.2
0
1 2 4 6 8 10 12
(VIN – VOUT) – Volts
Figure 12. Operating Frequency vs.
(VIN–VOUT)
155
MAXIMUM THRESHOLD
150
145
140
135
130
0
25 70 85
TEMPERATURE – ؇C
100
Figure 15. Current Sense Threshold
Voltage
3.36
3.34
3.32
3.30
3.28
VIN = 6 VOLTS
3.26
3.24
3.22
VIN = 12 VOLTS
3.20
3.18
0
400 800 1200 1600 2000
LOAD CURRENT – mA
Figure 18. Load Regulation (VO = 3.3 V);
Figure 1 Circuit with ADP1147-3.3
30
25
20
QN + QP = 100nC
15
10
5
QN + QP = 50nC
0
20 50 80 110 140 170 200 230 260
OPERATING FREQUENCY – kHz
Figure 13. Gate Charge Supply
Current
ADP1147-3.3/ADP1147-5
80
70
60
50
+5V
40
30
20
+3.3V
10
0
0.3 0.5 1 1.5 2 2.5 3 3.3 3.5 4 4.5 5
OUTPUT VOLTAGE – Volts
Figure 14. Off-Time vs. VOUT
95
90
1 AMP
85
0.1 AMP
80
75
70
5 8 11 14 17 20
INPUT VOLTAGE – Volts
Figure 16. Efficiency vs. Input
Voltage at VO = 3.3 V; Figure 1
Circuit with ADP1147-3.3
3.35
3.34
100mA
3.33
3.32
300mA
3.31
3.30
1 AMP
3.29
3.28
3.27
4
8 12
INPUT VOLTAGE – Volts
16
Figure 17. Output Voltage vs. Input
Voltage (VO = 3.3 V); Figure 1 Circuit
with ADP1147-3.3
REV. 0
–5–
5 Page 
To obtain optimum efficiency the required ESR value of COUT
is 100 mΩ or less.
The circuit should also be evaluated with the minimum input
voltage. This is done to assure that the power dissipation and
junction temperature of the P-channel MOSFET are not ex-
ceeded. At lower input voltages the operating frequency of the
ADP1147 decreases. This causes the P-channel MOSFET to
remain in conduction for longer periods of time, resulting in
more power dissipation in the MOSFET.
The effects of VIN(MIN) can be evaluated if we assume the
following:
VIN(MIN) = 4.5 V
VOUT = 3.3 V
VD = 0.4 V
fMIN = (1/3.15 µs) × (1– (3.7/4.9)) = 78 kHz.
PD
=
3.3 (0.125
Ω)(1 A)2
4.5
(1.2625 )
= 116
mW
Troubleshooting Hints
Efficiency is the primary reason for choosing the ADP1147 for
use in an application, and it is critical to determine that all por-
tions of the circuit are functioning properly in all modes. After
the design is complete the voltage waveforms on the timing
capacitor, CT, at Pin 2 of the device, should be compared to the
waveforms in Figures 19a and 19b.
In the continuous mode of operation the dc voltage level of the
waveform on CT should never fall below the 2 V level and it
should have a 0.9 V peak-to-peak sawtooth on it (see Figure
19a).
In the Power Savings Mode the sawtooth waveform on CT will
decay to ground for extended periods of time (see Figure 19b).
During the time that the capacitor voltage is at ground the
ADP1147 is in the power savings or sleep mode and the qui-
escent current is reduced to 160 µA typical.
The ripple current in the inductor should also be monitored to
determine that it is approximately the same in both modes of
operation. With a higher output currents the voltage level on CT
should never decay to ground as this would indicate poor
grounding and or decoupling.
ADP1147-3.3/ADP1147-5
Printed Wire Board Layout Considerations
The PWB layout is extremely critical for proper circuit opera-
tion and the items listed below should be carefully considered
(see Figure 20)
1. The signal and power grounds should be separate from each
other. They should be tied together only at ground Pin 7 of
the ADP1147. The power ground should be tied to the an-
ode of the Schottky diode, and the (–) side of the CIN capaci-
tor. The connections should be made with traces that are as
wide and as short as possible. The signal ground should be
connected to the (–) side of capacitor COUT using the same
type of runs as above.
2. The sense(–) run to Pin 4 of the ADP1147 should be con-
nected directly to the junction point of RSENSE and the + side
of COUT.
3. The sense(–) and sense(+) traces should be routed together
with minimum track spacing and run lengths. The 1000 pF
filter capacitor across Pins 4 and 5 of the ADP1147 should
be located as close to the device as possible.
4. In order to supply sufficient ac current the (+) side of capaci-
tor CIN should be connected with wide short traces and must
be located as close to the source of the P-MOSFET as possible.
5. In order to supply high frequency peak currents the input
decoupling capacitors should range from 0.1 µF to 1.0 µF
and must be located as close to the VIN pin and the ground
Pin 7 as possible.
6. The shutdown Pin (6) is a high impedance input and it must
not be allowed to float. The normal mode of operation of the
device requires that this pin be pulled low.
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP1147.PDF ] | |
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