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ADN2850 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2850
Beschreibung Nonvolatile Memory/ Dual 1024 Position Programmable Resistors
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 18 Seiten
ADN2850 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
a
Nonvolatile Memory, Dual 1024
Position Programmable Resistors
Preliminary Technical Data
ADN2850
FEATURES
Dual, 1024 Position Resolution
25K, 250K Ohm Full Scale Resistance
Low Temperature Coefficient -- 35ppm/°C
Nonvolatile Memory1 Preset Maintains Wiper Settings
Wiper Settings Read Back
Linear Increment/Decrement
Log taper Increment/Decrement
SPI Compatible Serial Interface
+3V to +5V Single Supply or ±2.5V Dual Supply
26 bytes User Nonvolatile Memory for Constant Storage with
Current Monitoring Configurable Function
APPLICATIONS
SONET, SDH, ATM, Gigabit Ethernet, DWDM Laser Diode
Driver Optical Supervisory Systems
GENERAL DESCRIPTION
The ADN2850 provides dual channel, digitally controlled
programmable resistors2 with resolution of 1024 positions. These
devices perform the same electronic adjustment function as a
mechanical rheostat. The ADN2850’s versatile programming via a
standard serial interface allows sixteen mode of operations and
adjustment including scratch pad programming, memory storing
and retrieving, increment/decrement, log taper adjustment, wiper
setting readback, and extra user defined EEMEM.
In the scratch pad programming mode, a specific setting can be
programmed directly to the RDAC2 register, which sets the
resistance between terminals W-and-B. The RDAC register can
also be loaded with a value previously stored in the EEMEM1
register. The value in the EEMEM can be changed or protected.
When changes are made to the RDAC register, the value of the new
setting can be saved into the EEMEM. Thereafter, such value will
be transferred automatically to the RDAC register during system
power ON. It is enabled by the internal preset strobe. EEMEM can
also be retrieved through direct programming and external preset
pin control.
Other key mode of operations include linear step increment and
decrement commands such that the setting in the RDAC register
can be moved UP or DOWN, one step at a time. For logarithmic
changes in wiper setting, a left/right bit shift command adjusts the
level in ±6dB steps.
The ADN2850 is available in the 5mm x 5mm LFCSP-16 Lead
Frame Chip Scale and thin TSSOP-16 packages. All parts are
guaranteed to operate over the extended industrial temperature
range of -40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SDO
ADDRE S S
DECO DE
SERIAL
INPUT
REG IS TE R
RD AC1
REGIST ER
EEMEM1
PR
PWR ON
PRESET
WP
R DY
EEMEM
CON TROL
VDD
VSS
GND
RD AC2
REGIST ER
EEMEM2
26 BYTES
USER EEMEM
RD AC1
W1
B1
RD AC1
W2
B2
I1
C URRENT
M ON IT OR
I2
V1
V2
100%
75%
50%
25%
0%
0
256 512 768
D - Co d e in De cim al
Figure 1. RWB(D) vs Decimal Code
1023
Notes:
1. The term nonvolatile memory and EEMEM are used interchangebly
2. The term programmable resistor and RDAC are used interchangebly
REV PrH, 13, AUG 2001
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or
other rights of third parties which may result from its use. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 617/329-4700
Fax:617/326-8703






ADN2850 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
ADN2850
ADN2850ACP PIN CONFIGURATION
ADN2850ARU PIN CONFIGURATION
SDO 1
GND 2
VSS 3
V1 4
SDI CLK RDY CS
16 15 14 13
5678
W1 B1 B2 W2
12 PR
11 WP
10 VDD
9 V2
CLK 1
SDI 2
SDO 3
GND 4
VSS 5
V1 6
W1 7
B1 8
16 RDY
15 CS
14 PR
13 WP
12 VDD
11 V2
10 W2
9 B2
ADN2850ACP PIN DESCRIPTION
ADN2850ARU PIN DESCRIPTION
# Name
1 SDO
2 GND
3 VSS
4 V1
5 W1
6 B1
7 B2
8 W2
9 V2
10 VDD
11 WP
12 PR
13 CS
14 RDY
15 CLK
16 SDI
Description
Serial Data Output Pin. Open Drain Output requires
external pull-up resistor. Commands 9 and 10
activate the SDO output. See Instruction operation
Truth Table. Table 2. Other commands shift out the
previously loaded SDI bit pattern delayed by 24
clock pulses. This allows daisy-chain operation of
multiple packages.
Ground pin, logic ground reference
Negative Supply. Connect to zero volts for single
supply applications.
Log Output Voltage 1 generated from internal diode
configured transistor
Wiper terminal of RDAC1. ADDR(RDAC1) = 0H.
B terminal of RDAC1
B terminal of RDAC2.
Wiper terminal of RDAC2. ADDR(RDAC2) = 1H.
Log Output Voltage 2 generated from internal diode
configured transistor
Positive Power Supply Pin.
Write Protect Pin. When active low, WP prevents
any changes to the present register contents, except
PR and cmd 1 and 8 will refresh the RDAC register
from EEMEM.
Hardware over ride preset pin. Refreshes the scratch
pad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until
EEMEM loaded with a new value by the user (PR is
activated at the logic high transition).
Serial Register chip select active low. Serial register
operation takes place when CS returns to logic high.
Ready. Active-high open drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and PR.
Serial Input Register clock pin. Shifts in one bit at a
time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on
positive clock CLK edges. MSB loaded first.
# Name
1 CLK
2 SDI
3 SDO
4 GND
5 VSS
6 V1
7 W1
8 B1
9 B2
10 W2
11 V2
12 VDD
13 WP
14 PR
15 CS
16 RDY
Description
Serial Input Register clock pin. Shifts in one bit at a
time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on
positive clock CLK edges. MSB loaded first.
Serial Data Output Pin. Open Drain Output requires
external pull-up resistor. Commands 9 and 10
activate the SDO output. See Instruction operation
Truth Table. Table 2. Other commands shift out the
previously loaded SDI bit pattern delayed by 24
clock pulses. This allows daisy-chain operation of
multiple packages
Ground pin, logic ground reference
Negative Supply. Connect to zero volts for single
supply applications.
Log Output Voltage 1 generated from internal diode
configured transistor
Wiper terminal of RDAC1. ADDR(RDAC1) = 0H.
B terminal of RDAC1
B terminal of RDAC2.
Wiper terminal of RDAC2. ADDR(RDAC2) = 1H.
Log Output Voltage 2 generated from internal diode
configured transistor
Positive Power Supply Pin.
Write Protect Pin. When active low, WP prevents
any changes to the present contents except PR and
cmd 1 and 8 will refresh the RDAC register from
E2MEM.
Hardware over ride preset pin. Refreshes the scratch
pad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until
EEMEM loaded with a new value by the user (PR is
activated at the logic high transition).
Serial Register chip select active low. Serial register
operation takes place when CS returns to logic high.
Ready. Active-high open drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and PR.
REV PrH, 13, AUG 2001
6

6 Page









ADN2850 pdf, datenblatt
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
Note that in the zero-scale condition a finite wiper resistance of
50is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20mA to avoid
degradation or possible destruction of the internal switches.
The typical distribution of full scale RWB from channel-to-
channel matches to ±0.2% within the same package. Device to
device matching is process lot dependent with the worst case of
±30% variation. On the other hand, the change in RWB with
temperature has a 35ppm/°C temperature coefficient.
TEST CIRCUITS
Figures 10 to 12 show some of the test conditions used in the
product specification table.
ADN2850
Figure 10. Resistor Position Nonlinearity Error (Rheostat Operation; R-
INL, R-DNL)
Figure 11. Incremental ON Resistance Test Circuit
Figure 12. Common Mode Leakage current test circuit
REV PrH, 13, AUG 2001
12

12 Page





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