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PDF ADMCF341 Data sheet ( Hoja de datos )
| Número de pieza | ADMCF341 | |
| Descripción | DashDSP 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a DashDSP™ 28-Lead Flash Mixed-Signal DSP
with Enhanced Analog Front End
ADMCF341
FEATURES
20 MHz Fixed-Point DSP Core
Single-Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units
ALU, Multiplier/Accumulator, Barrel Shifter
Multifunction Instructions
Single-Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 16-Bit Data Memory RAM
512 ؋ 24-Bit Program Memory RAM
4K ؋ 24-Bit Program Memory ROM
4K ؋ 24-Bit Program Flash Memory
Three Independent Flash Memory Sectors
3584 ؋ 24-Bit, 256 ؋ 24-Bit, 256 ؋ 24-Bit
Low-Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode Support
Integrated Power-On Reset Function
Three-Phase 16-Bit PWM Generation Unit:
16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution to 50 ns
153 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Individual Enable and Disable for Each PWM Output
High-Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated 6-Channel ADC Subsystem
Three Bipolar ISENSE Inputs with Programmable
Sample-and-Hold Amplifier and Overcurrent Pro-
tection (Usable as Three Dedicated Analog Inputs)
Muxed Auxiliary Analog Inputs
Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching
Frequency
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 16-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
Motor Types
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
AC Induction Motors (ACIM)
APPLICATIONS
Refrigerator and Air Conditioner Compressor
Washing Machines
Industrial Variable Speed Drives
HVAC
FUNCTIONAL BLOCK DIAGRAM
ADSP-21xx BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY BLOCK
PROGRAM PROGRAM
ROM
FLASH
4K x 24
4K x 24
PROGRAM
RAM
512 x 24
DATA
MEMORY
512 x 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
MOTOR CONTROL PERIPHERALS
ADC SUBSYSTEM
3
VREF
2.5V
3
ANALOG
INPUTS
ISENSE AMP
AND TRIP
SHA
TIMERS
6
16-BIT
THREE-
PHASE
PWM
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
DashDSP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
SERIAL PORT
SPORT 0
SPORT 1
7
2 x 16-BIT
PIO AUX
PWM
92
MULTIPLEXED ON EXTERNAL PINS
WATCH-
DOG
TIMER
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
TIMING PARAMETERS
Parameter
Serial Ports
Timing Requirements
tSCK SCLK Period
tSCS DR/TFS/RFS Setup before SCLK Low
tSCH DR/TFS/RFS Hold after SCLK Low
tSCP SCLKIN Width
Switching Characteristics
tCC
tSCDE
tSCDV
tRH
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
tRD
tSCDH
tSCDD
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
SCLK High to DT Disable
tTDE TFS (Alt) to DT Enable
tTDV TFS (Alt) to DT Valid
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid
Specifications subject to change without notice.
Min
100
15
20
40
0.25 tCK
0
0
0
0
ADMCF341
Max
Unit
0.25 tCK + 20
30
30
30
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
SCLK
DR
RFSIN
TFSIN
RFSOUT
TFSOUT
DT
TFS
(ALTERNATE
FRAME MODE)
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
tCC tCC
tSCS tSCH
t SCK
t SCP
t SCP
t RD
t RH
t SCDE
t SCDV
t TDE
t TDV
t SCDH
t SCDD
t RDV
Figure 2. Serial Port Timing
REV. 0
–5–
5 Page 
The ADMCF341 sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT register,
and performs a full reset of all of the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET pin low.
The RESET signal must be the minimum pulsewidth specifica-
tion, tRSP. Following the reset sequence, the DSP core starts
executing code from the internal PM ROM located at 0x0800.
DSP Control Registers
The DSP core has a system control register, SYSCNTL,
memory-mapped at DM (0x3FFF). SPORT1 must be configured
as a serial port by setting Bit 10. SPORT0 and SPORT1 are
enabled by setting Bit 11 and Bit 12.
The DSP core has a wait state control register, MEMWAIT,
memory-mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMCF341,
this register must always contain the value 0x8000. This value
sets the minimum access time to the program memory.
The configurations of both the SYSCNTL and MEMWAIT regis-
ters of the ADMCF341 are shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMCF341 is a flexible,
programmable three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction
motors (ACIM) or permanent magnet synchronous motors
(PMSM). In addition, the PWM block contains special func-
tions that considerably simplify the generation of the required
ADMCF341
PWM switching patterns for control of brushless dc motors
(BDCM), including electronically commutated motors (ECM).
The six PWM output signals consist of three high side drive
signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are pro-
grammable using, respectively, the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the
three pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the high side PWM signals
are diverted to the complementary low side output and the low
side signals are diverted to the corresponding high side outputs.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques: optical isolation using optocouplers, and trans-
former isolation using pulse transformers. The PWM controller
of the ADMCF341 permits mixing of the output PWM signals
with a high-frequency chopping signal to permit an easy inter-
face to such pulse transformers. The features of this gate-drive
chopping mode can be controlled by the PWMGATE register.
There is an 8-bit value within the PWMGATE register that
directly controls the chopping frequency. In addition, high-
frequency chopping can be independently enabled for the high
side and the low side outputs using separate control bits in the
PWMGATE register.
PWM CONFIGURATION
REGISTERS
PWMTM (15...0)
PWMDT (9...0)
PWMPD (9...0)
PWMSYNCWT (7...0)
MODECTRL (6)
PWM DUTY CYCLE
REGISTERS
PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)
PWMSEG (8...0)
PWMGATE (9...0)
THREE-PHASE
PWM TIMING
UNIT
CLK SYNC RESET
PWMSYNC
TO INTERRUPT
CONTROLLER
PWMTRIP
OUTPUT
CONTROL
UNIT
SYNC
GATE
DRIVE
UNIT
CLK
AH
AL
BH
BL
CH
CL
CLKOUT
OR
PWMSWT (0)
PWM SHUTDOWN CONTROLLER
PWMTRIP
OVER-
CURRENT
TRIP
ISENSE1
ISENSE2
ISENSE3
ANALOG BLOCK
Figure 6. Overview of the PWM Controller of the ADMCF341
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADMCF341.PDF ] | |
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