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ADMCF340BST Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADMCF340BST
Beschreibung DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADMCF340BST Datasheet, Funktion
a DashDSPTM 64-Lead Flash Mixed-Signal DSP
with Enhanced Analog Front End
ADMCF340
TARGET APPLICATIONS
Refrigerator and Air Conditioner Compressors,
Washing Machines
Industrial Variable Speed Drives, HVAC
MOTOR TYPES
Permanent Magnet Synchronous Motors (PMSM),
Brushless DC Motors (BDCM), AC Induction Motors
(ACIM), Switched Reluctance Motors (SRM)
FEATURES
20 MHz Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 16-Bit Data Memory RAM
512 ؋ 24-Bit Program Memory RAM
4K ؋ 24-Bit Program Memory ROM
4K ؋ 24-Bit Total Program FLASH Memory
Three Independent FLASH Memory Sectors
3584 ؋ 24-Bit, 256 ؋ 24-Bit, 256 ؋ 24-Bit
Low Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode
Support
Integrated Power On Reset Function
Three Phase 16-Bit PWM Generation Unit
16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution of 50 ns
Programmable Narrow Pulse Deletion
153 Hz Minimum Switching Frequency
Double/Single Update Mode Control
Individual Enable and Disable for Each PWM
Output
High Frequency Chopping Mode for
Transformer-Coupled Gate Drives
(continued on page 8)
FUNCTIONAL BLOCK DIAGRAM
ADSP-21xx BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY BLOCK
PROGRAM
ROM
4K ؋ 24
PROGRAM
RAM
512 ؋ 24
PROGRAM
FLASH
4K ؋ 24
DATA
MEMORY
512 ؋ 16
PROGRAM MEMORY ADDRESS
MOTOR CONTROL PERIPHERALS
ADC SUBSYSTEM
10
VREF
2.5V
ANALOG
INPUTS
3
ISENSE AMP
AND TRIP
SHA
TIMERS
6
16-BIT
THREE-
PHASE
PWM
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
SERIAL PORT
SPORT 0
SPORT 1
7
2 ؋ 16-BIT
PIO AUX
PWM
25 2
WATCH-
DOG
TIMER
DashDSP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accu-
rate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents
or other rights of third parties that may result from its use. No
license is granted by implication or otherwise under any patent
or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






ADMCF340BST Datasheet, Funktion
ADMCF340
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATION
AGND 1
DGND1 2
RESET 3
PB6 4
CH 5
PB7 6
PB8 7
CL 8
PB9 9
PB10 10
BH 11
PB11 12
PB12 13
BL 14
NC 15
NC 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1
IDENTIFIER
ADMCF340
TOP VIEW
(Not to Scale)
48 AVDD
47 DVDD1
46 XTAL
45 NC
44 CLKIN
43 NC
42 PB5
41 PB4
40 PA0/DR0
39 PB3
38 PB2
37 PA1/DT0
36 PB1
35 PB0
34 PA2/RFS0
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Model
ADMCF340BST
ADMCF340-EVALKIT
Temperature
Range
–40°C to +85°C
N/A
ORDERING GUIDE
Instruction
Rate
Package
Description
20 MHz
N/A
64-Lead Thin Plastic Quad Flatpack
(LQFP)
Development Tool Kit
Package
Option
ST-64
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADMCF340 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. 0

6 Page









ADMCF340BST pdf, datenblatt
ADMCF340
Reset
The ADMCF340 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper unitization.
The ADMCF340 contains an integrated power-on-reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMCF340 VDD Pin and holds the DSP core and peripherals
in reset while VDD is less than the threshold voltage level, VRST.
When this voltage is exceeded, the ADMCF340 is held in reset
for an additional 216 DSP clock cycles (TRST in Figure 5). During
this time (TRST), the supply voltage must reach the recommended
operating condition. On power-down, when the voltage on the
VDD Pin falls below VRST –VHYST, the ADMCF340 will be
reset. Also, if the external RESET Pin is actively pulled low
at any time after power-up, a complete hardware reset of the
ADMCF340 is initiated.
VRST
VDD
VRST VHYST
RESET
TRST
Figure 5. Power-On Reset Operation
The ADMCF340 sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT Register,
and performs a full reset of all the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET Pin low.
The RESET signal must be the minimum pulsewidth specification,
tRSP. Following the reset sequence, the DSP core starts executing
code from the internal PM ROM located at 0x0800.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory-
mapped at DM (0x3FFF). SPORT1 must be configured as a
serial port by setting Bit 10. SPORT0 and SPORT1 are enabled
by setting Bit 11 and Bit 12.
The DSP core has a wait state control register, MEMWAIT,
memory-mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMCF340,
this register must always contain the value 0x8000. This value
sets the minimum access time to the program memory.
The configurations of both the SYSCNTL and MEMWAIT Reg-
isters of the ADMCF340 are shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMCF340 is a flexible,
programmable, three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction motors
(ACIM) or permanent magnet synchronous motors (PMSM).
In addition, the PWM block contains special functions that
considerably simplify the generation of the required PWM
switching patterns for control of electronically commutated
motors (ECM), brushless dc motors (BDCM), or switched
reluctance motors (SRM).
The six PWM output signals consist of three high side drive
signals (AH, BH, and CH) and three low side drive signals (AL,
BL, and CL). The switching frequency, dead time, and minimum
pulsewidths of the generated PWM patterns are programmable
using, respectively, the PWMTM, PWMDT, and PWMPD
registers. In addition, three registers (PWMCHA, PWMCHB,
and PWMCHC) control the duty cycles of the three pairs of
PWM signals.
PWM CONFIGURATION
REGISTERS
PWMTM (15...0)
PWMDT (9...0)
PWMPD (9...0)
PWMSYNCWT (7...0)
MODECTRL (6)
PWM DUTY CYCLE
REGISTERS
PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)
PWMSEG (8...0)
PWMGATE (9...0)
THREE-PHASE
PWM TIMING
UNIT
CLK SYNC RESET
PWMSYNC
TO INTERRUPT
CONTROLLER
PWMTRIP
OUTPUT
CONTROL
UNIT
SYNC
OR
GATE
DRIVE
UNIT
CLK
AH
AL
BH
BL
CH
CL
CLKOUT
PWMTRIP
PWMSWT (0)
PWM SHUTDOWN CONTROLLER
OVER
CURRENT
TRIP
ISENSE1
ISENSE2
ISENSE3
ANALOG BLOCK
Figure 6. Overview of the PWM Controller of the ADMCF340
–12–
REV. 0

12 Page





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