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ADMC401 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADMC401
Beschreibung Single-Chip/ DSP-Based High Performance Motor Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADMC401 Datasheet, Funktion
a
Single-Chip, DSP-Based
High Performance Motor Controller
ADMC401
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-21xx Family Code Compatible
16-Bit Arithmetic and Logic Unit (ALU)
Single Cycle 16-Bit ؋ 16-Bit Multiply and Accumulate
Into 40-Bit Accumulator (MAC)
32-Bit Shifter (Logical and Arithmetic)
Multifunction Instructions
Single Cycle Context Switch
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
2K ؋ 24-Bit Internal Program Memory RAM
2K ؋ 24-Bit Internal Program Memory ROM
1K ؋ 16-Bit Internal Data Memory RAM
14-Bit Address Bus and 24-Bit Data Bus for External
Memory Expansion
High Resolution Multichannel ADC
12-Bit Pipeline Flash Analog-to-Digital Converter
Eight Dedicated Analog Inputs
Simultaneous Sampling Capability
All Eight Inputs Converted in <2 s
4.0 V p-p Input Voltage Range
PWM Synchronized or External Convert Start
Internal or External Voltage Reference
Out-of-Range Detection
Voltage Reference
Internal 2.0 V ؎ 2.0% Voltage Reference
Three-Phase 16-Bit PWM Generation Unit
Programmable Switching Frequency, Dead Time and
Minimum Pulsewidth
Edge Resolution of 38.5 ns
One or Two Updates per Switching Period
Hardware Polarity Control
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Dedicated Shutdown Pin (PWMTRIP)
Additional Shutdown Pins in I/O System
High Output Sink and Source Capability (10 mA)
Incremental Encoder Interface Unit
Quadrature Rates to 17.3 MHz
Programmable Filtering of Encoder Inputs
Alternative Frequency and Direction Mode
Two Registration Inputs to Latch Count Value
Optional Hardware Reset of Counter
Single North Marker Mode
Count Error Monitor Function
Dedicated 16-Bit Loop Timer (Periodic Interrupts)
Companion Encoder Event (1/T) Timer
(Continued on Page 14)
FUNCTIONAL BLOCK DIAGRAM
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
26 MIPS DSP CORE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PM
ROM
2K ؋ 24
PM
RAM
2K ؋ 24
MEMORY
DM
RAM
1K ؋ 16
MOTOR CONTROL
PERIPHERALS
WATCH-
DOG
TIMER
POWER-
ON
RESET
INTERRUPT
CONTROLLER
ENCODER
INTERFACE
EVENT
CAPTURE
UNIT
DIGITAL
I/O
UNIT
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
INTERVAL
SPORT 0 SPORT 1
TIMER
2 CHANNEL
AUXILIARY
PWM
8 CHANNEL
12-BIT ADC
PRECISION
VOLTAGE
REFERENCE
16-BIT
PWM
GENERATION
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADMC401 Datasheet, Funktion
ADMC401
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirements:
tIFS IRQx or FI Setup before CLKOUT Low1, 2, 3
tIFH IRQx or FI Hold after CLKOUT High1, 2, 3
Switching Characteristics:
tFOH Flag Output Hold after CLKOUT Low4
tFOD Flag Output Delay from CLKOUT Low4
0.25tCK + 15
0.25tCK
0.5tCK – 7
0.5tCK + 5
ns
ns
ns
ns
NOTES
1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition for further
information on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3IRQx = IRQ0 and IRQ1.
4Flag Output = FL1 and FO.
CLKOUT
FLAG
OUTPUTS
IRQx
FI
t FOD
t FOH
t IFH
t IFS
Figure 2. Interrupts and Flags
–6– REV. B

6 Page









ADMC401 pdf, datenblatt
ADMC401
PIN FUNCTION DESCRIPTION
Pin Pin
No. Name
Pin
No.
1 A9
37
2 A8
38
3 A7
39
4 A6
40
5 VDD
41
6 A5
42
7 A4
43
8 A3
44
9 GND
45
10 A2
46
11 A1
47
12 A0
13 PWD
48
49
14
PWDACK
50
15 BR
51
16 NC
52
17 NC
53
18
BMODE
54
19 MMAP
55
20 VDD
56
21 GND
57
22 PWMSR 58
23 POR
59
24 RESET
60
25 GND
61
26 GND
62
27 GND
63
28
PWMPOL
64
29 CLKIN
65
30 XTAL
66
31
CLKOUT
67
32 VDD
68
33 GND
69
34
DR1A/FI
70
35 DRIB/FI 71
36 DT1/FO 72
NC: These pins must be left unconnected
Pin
Name
RFS1/IRQ0/SROM
TFS1/IRQ1
SCLK1
DR0
DT0
RFS0
TFS0
SCLK0
VDD
GND
PWMTRIP
PWMSYNC
CL
CH
VDD
GND
BL
BH
AL
AH
BGH
D23
D22
D21
D20
D19
GND
D18
D17
D16
D15
D14
D13
D12
VDD
D11
Pin
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Pin Pin Pin
Name No. Name
GND
D10
D9
D8
D7
D6
D5
D4
D3
GND
D2
D1
D0
P11
P10
P9
P8
VDD
GND
P7
P6
P5
P4
P3
P2
GND
P1
P0
AUX1
AUX0
ETU1
ETU0
EIS
EIZ
EIB
EIA
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
CONVST
GND
VDD
GND
AVDD
AVSS
VIN7
VREF
VIN6
REFCOM
VIN5
CAPT
VIN4
BSHAN
ASHAN
VIN0
CAPB
VIN1
CML
VIN2
GAIN
VIN3
SENSE
AVSS
AVDD
BMS
PMS
DMS
RD
GND
BG
WR
A13
A12
A11
A10
–12–
REV. B

12 Page





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