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ADMC331 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADMC331
Beschreibung Single Chip DSP Motor Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADMC331 Datasheet, Funktion
a
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generator
Memory Configuration
2K ؋ 24-Bit Program Memory RAM
2K ؋ 24-Bit Program Memory ROM
1K ؋ 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Deadtime and Narrow Pulse Deletion
Single Chip DSP
Motor Controller
ADMC331
Edge Resolution to 38.5 ns
198 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Suitable for AC Induction and Synchronous Motors
Special Signal Generation for Switched Reluctance
Motors
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for all PWM Outputs
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
Hardwired Polarity Control
External PWMTRIP Pin
Seven Analog Input Channels
Acquisition Synchronized to PWM Switching
Frequency
Conversion Speed Control
24 Bits of Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synchronized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
FUNCTIONAL BLOCK DIAGRAM
(Continued on page 7)
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
2K ؋ 24
PROGRAM
RAM
2K ؋ 24
MEMORY
DATA
RAM
1K ؋ 16
WATCH-
DOG
TIMER
24-BIT
PIO
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
2 ؋ 8 BIT
AUX
PWM
7
ANALOG
INPUTS
16-BIT
3-PHASE
PWM
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADMC331 Datasheet, Funktion
ADMC331
PIN FUNCTION DESCRIPTIONS
Pin Pin
No. Type
1 O/P
2 SUP
3 GND
4 BIDIR
5 BIDIR
6 BIDIR
7 BIDIR
8 BIDIR
9 BIDIR
10 BIDIR
11 BIDIR
12 BIDIR
13 BIDIR
14 O/P
15 O/P
16 BIDIR
17 BIDIR
18 SUP
19 I/P
20 GND
Pin
Name
VREF
AVDD
GND
PIO9
PIO8
PIO7
PIO6
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
AUX1
AUX0
PIO10
PIO11
VDD
PWMTRIP
GND
Pin Pin Pin
No. Type Name
21 SUP VDD
22 GND GND
23 BIDIR PIO12
24 BIDIR PIO13
25 O/P PWMSYNC
26 O/P CL
27 O/P CH
28 O/P BL
29 O/P BH
30 O/P AL
31 O/P AH
32 BIDIR PIO14
33 BIDIR PIO15
34 BIDIR PIO16
35 SUP VDD
36 GND GND
37 BIDIR PIO17
38 GND GND
39 BIDIR PIO18
40 GND GND
Pin Pin
No. Type
41 GND
42 GND
43 O/P
44 I/P
45 I/P
46 I/P
47 GND
48 SUP
49 BIDIR
50 BIDIR
51 O/P
52 GND
53 O/P
54 BIDIR
55 BIDIR
56 I/P
57 I/P
58 BIDIR
59 O/P
60 I/P
Pin
Name
GND
GND
XTAL
CLKIN
PWMPOL
RESET
GND
VDD
PIO19
PIO20
CLKOUT
GND
DT1
TFS1
RFS1/SROM
DR1A
DR1B
SCLK1
DT0
PWMSR
Pin Pin Pin
No. Type Name
61 BIDIR TFS0
62 BIDIR RFS0
63 I/P
DR0
64 BIDIR SCLK0
65 BIDIR PIO21
66 BIDIR PIO22
67 BIDIR PIO23
68 SUP VDD
69 GND GND
70 GND AGND
71 I/P
CAPIN
72 O/P ICONST
73 GND SGND
74 I/P
V1
75 I/P
V2
76 I/P
V3
77 I/P
VAUX0
78 I/P
VAUX1
79 I/P
VAUX2
80 I/P
VAUX3
PIN CONFIGURATION
80-Lead Plastic Thin Quad Flatpack (TQFP)
(ST-80)
VREF 1
AVDD
GND
PIO9
2
3
4
PIO8 5
PIO7 6
PIO6 7
PIO5 8
PIO4 9
PIO3 10
PIO2 11
PIO1 12
PIO0 13
AUX1 14
AUX0 15
PIO10 16
PIO11 17
VDD 18
PWMTRIP 19
GND 20
PIN 1
IDENTIFIER
ADMC331
TOP VIEW
(Not to Scale)
60 PWMSR
59 DT0
58 SCLK1
57 DR1B
56 DR1A
55 RFS1/ SROM
54 TFS1
53 DT1
52 GND
51 CLKOUT
50 PIO20
49 PIO19
48 VDD
47 GND
46 RESET
45 PWMPOL
44 CLKIN
43 XTAL
42 GND
41 GND
–6– REV. B

6 Page









ADMC331 pdf, datenblatt
ADMC331
Boot Loading
On power-up or reset, the ADMC331 is configured so that
execution begins at the internal PM ROM at address 0x0800.
This starts execution of the internal monitor function that first
performs some initialization functions and copies a default inter-
rupt vector table to addresses 0x0000–0x002F of program memory
RAM. The monitor next attempts to boot load from an external
SROM or E2PROM on SPORT1 using the three wire connec-
tion of Figure 4. The monitor program first toggles the RFS1/
SROM pin of the ADMC331 to reset the serial memory device.
If an SROM or E2PROM is connected to SPORT1, data is
clocked into the ADMC331 at a rate CLKOUT/20. Both pro-
gram and data memory RAM can be loaded from the SROM or
E2PROM. After the boot load is complete, program execution
begins at address 0x0030. This is where the first instruction of
the user code should be placed.
If boot loading from an E2PROM is unsuccessful, the monitor
code reconfigures SPORT1 as a UART and attempts to receive
commands from an external device on this serial port. The
monitor then waits for a byte to be received over SPORT1,
locks onto the baud rate of the external device (autobaud fea-
ture) and takes in a header word that tells it with what type of
device it is communicating. There are six alternatives:
• A UART boot loader such as a Motorola 68HC11SCI port.
• A synchronous slave boot loader (the clock is external).
• A synchronous master boot loader (the ADMC331 provides the
clock).
• A UART debugger interface.
• A synchronous master debugger interface.
• A synchronous slave debugger interface.
With the debugger interface, the monitor enters an interactive
mode in which it processes commands received from the exter-
nal device.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is
set, disabled when this bit is cleared. SPORT1 is enabled when
Bit 11 is set, disabled when this bit is cleared. SPORT1 is con-
figured as a serial port when Bit 10 is set, or as flags and inter-
rupt lines when this bit is cleared. For proper operation of the
ADMC331, all other bits in this register must be cleared (which
is their default).
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). For proper operation of the
ADMC331, this register must always contain the value 0x8000
(which is the default).
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC331 is shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMC331 is a flexible, pro-
grammable, three-phase PWM waveform generator that can be
programmed to generate the required switching patterns to drive
a three-phase voltage source inverter for ac induction (ACIM),
or permanent magnet synchronous (PMSM) or a switched or
variable reluctance (SRM) motor control. In addition, the
PWM block contains special functions that considerably sim-
plify the generation of the required PWM switching patterns for
control of the electronically commutated motor (ECM) or
brushless dc motor (BDCM).
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (AH, AL, BH, BL, CH and CL). The
six PWM output signals consist of three high side drive signals
(AH, BH and CH) and three low side drive signals (AL, BL and
CL). The polarity of the generated PWM signals may be
programmed by the PWMPOL pin, so that either active HI or
active LO PWM patterns can be produced by the ADMC331.
The switching frequency, dead time and minimum pulsewidths
of the generated PWM patterns are programmable using respec-
tively the PWMTM, PWMDT and PWMPD registers. In addi-
tion, three duty cycle control registers (PWMCHA, PWMCHB
and PWMCHC) directly control the duty cycles of the three
pair of PWM signals.
When the PWMSR pin is pulled low, the PWM generator trans-
forms the six PWM output signals into six waveforms for
switched reluctance gate drive signals. The low side PWM
signals from the three-phase timing unit assume permanently
ON states, independent of the value written to the duty-cycle
registers. The duty cycles of the high side PWM signals from the
timing unit are still determined by the three duty-cycle registers.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques, optical isolation using opto-couplers, and trans-
former isolation using pulse transformers. The PWM controller
of the ADMC331 permits mixing of the output PWM signals
with a high frequency chopping signal to permit easy interface to
such pulse transformers. The features of this gate-drive chop-
ping mode can be controlled by the PWMGATE register. There
is an 8-bit value within the PWMGATE register that directly con-
trols the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low side
outputs using separate control bits in the PWMGATE register.
The PWM generator is capable of operating in two distinct
modes, single update mode or double update mode. In single
update mode, the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
update mode, a second updating of the PWM duty cycle values
is implemented at the midpoint of the PWM period. In this
mode, it is possible to produce asymmetrical PWM patterns,
that produce lower harmonic distortion in three-phase PWM
inverters. This technique also permits the closed loop controller
to change the average voltage applied to the machine winding at
a faster rate and so permits fast closed loop bandwidths to be
achieved. The operating mode of the PWM block (single or
double update mode) is selected by a control bit in MODECTRL
register.
–12–
REV. B

12 Page





SeitenGesamt 30 Seiten
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