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PDF ADMC330BST Data sheet ( Hoja de datos )
| Número de pieza | ADMC330BST | |
| Descripción | Single Chip DSP Motor Controller | |
| Fabricantes | Analog Devices | |
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a
Single Chip DSP
Motor Controller
ADMC330
FEATURES
Seven Analog Input Channels
Acquisition Synchronized to PWM Switching Frequency
Three-Phase 12-Bit PWM Generator
Programmable Deadtime and Narrow Pulse Deletion
2.5 kHz Minimum Switching Frequency
ECM Control Mode
Output Control for Space Vector Modulation
Gate Drive Block (Pulsed PWM Output Capability)
Hardwired Output Polarity Control
External Trip Input
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
39 kHz Frequency
0 to 99.6% Duty Cycle
Eight Bits of Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
20 MIPS Fixed Point DSP Core
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single-Cycle Instruction Execution (50 ns)
Single-Cycle Context Switch
ADSP-2100 Family Code and Function Compatible with
Instruction Set Enhancements
16-Bit Watchdog Timer
Programmable 16-Bit Interval Timer with Prescaler
Two Synchronous Serial Ports
Full Debugger Interface
2 Bootstrap Protocols via Sport 1, Serial and UART
Memory Configuration
2K ؋ 24-Bit Word Program RAM
1K ؋ 16-Bit Word Data RAM
2K ؋ 24-Bit Word Program ROM
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
2K ؋ 24
PROGRAM
RAM
2K ؋ 24
MEMORY
DATA
MEMORY
1K ؋ 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
WATCH-
DOG
TIMER
8-BIT
PIO
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
2 ؋ 8-BIT
AUX
PWM
ANALOG
INPUTS
12-BIT
3-PHASE
PWM
GENERAL DESCRIPTION
The ADMC330 is a low cost single chip DSP microcontroller
optimized for stand alone ac motor control applications. The
device is based on a 20 MHz fixed-point DSP core (ADSP-
2171) and a set of motor control peripherals including seven
analog input channels and a 12-bit three-phase PWM generator.
The device has two auxiliary 8-bit PWM channels and adds
expansion capability through the serial ports and an 8-bit digital
I/O port. The ADMC330 has internal 2K words program RAM,
and 1K words data RAM, which can be loaded from an external
device via the serial port. There are also 2K words of internal
program ROM, which includes a monitor that adds software
debugging features through the serial port.
The ADMC330 core combines the ADSP-2100 base architec-
ture (three computational units, data address generators and a
program sequencer) with two serial ports, a programmable
timer, extensive interrupt capabilities and on-chip program and
data memory.
In addition, the ADMC330 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding and global interrupt masking, for increased
flexibility.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
1 page  
ADMC330
The ADMC330 operates with a 50 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The flexible architecture and comprehensive instruction set of
the ADMC330 allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADMC330 can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
This takes place while the processor continues to:
• receive and transmit data through the two serial ports
• decrement the timer
an executable file. The simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
MAKEPROM utility splitter generates PROM programmer
compatible files. The C Compiler, based on the Free Software
Foundation’s GNU C Compiler, generates ADMC330 assem-
bly source code. The runtime library includes over 100 ANSI-
standard mathematical and DSP-specific functions.
Low cost, easy-to-use hardware development tools include an
ADMC330-EVAL board and a windows based software debugger.
This debugger can be run with either the ADMC330-EVAL
board or the target system by communicating over a two-wire
asynchronous link to a PC.
Independently the peripheral blocks can:
• generate three-phase PWM waveforms for a power inverter
• generate two signals using the 8-bit auxiliary PWM timers
• acquire four analog signals
• control eight digital I/O lines
• decrement the watchdog timer
ROM Code Functions
The ADMC330 has a 2K Boot ROM that contains the
following:
• Monitor Program:
Serial Boot Loader for OTP ROM or EEPROM
UART Debugger Interface and Loader
• Math Utilities/Tables:
Sine, cosine, tangent, inverse tangent, log, inverse log,
square root, 1/X, 1/(sine rms), unsigned division, Cartesian
to polar conversion, interpolation
The ADMC330 is similar to an ADSP-2172 in its booting se-
quence. The MMAP and BMODE pins are tied high, which
enables the on-chip ROM and starts execution of the monitor
program on power-up or reset. The monitor program first at-
tempts to boot load through SPORT1 from a serial memory
device. The loader uses a two-wire (data and clock) serial proto-
col. The ADMC330 provides a serial clock to the device equal
to 1/20 of CLKOUT. Default input is from a Xilinx XC1765D
OTP ROM or Atmel AT17C65 EEPROM; other devices are
possible as long as they adhere to the loader protocol. If the
serial load is successful, the code that was downloaded is ex-
ecuted at the start of user memory space.
Failing a synchronous boot load, the ADMC330 monitor switches
over to debug mode and waits for commands over SPORT1
from a UART. Debug mode uses a standard RS-232 protocol in
which only the data receive and transmit lines are used by the
ADMC330. This interface is used by the Visual DSP® Debugger,
but can also be used by UART devices for boot loading programs.
In addition to the monitor program, the ROM contains the
previously listed math utilities. These routines can be called
from user applications.
Development System
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADMC330. The system builder provides a high level
method for defining the architecture of systems under develop-
ment. The assembler has an algebraic syntax that is easy to
program and debug. The linker combines object files into
Visual DSP is a registered trademark of Analog Devices, Inc.
FUNCTIONAL DESCRIPTION
ADMC330 Peripherals Overview
The ADMC330 set of peripherals was specifically developed to
address the requirements of variable speed control of ac induc-
tion motors (ACIM) and electronically commutated synchro-
nous motors (ECM). They are memory mapped to a block in
the DSP data memory space allowing single cycle read and/or
write to all peripheral registers. The operation of the peripherals
is synchronized to the DSP core by a clock HCLK, which is
derived from half of the DSP system clock.
Three-Phase PWM Generator
• 12-bit center-based PWM generator including program-
mable deadtime and narrow pulse deletion.
• ECM crossover block.
• Output enable block.
• Hardwired output polarity control.
• External trip input.
• Pulsed PWM output capability for transformer coupled gate.
Analog I/O
• Two 8-bit PWM Output Timers—(Synthesized Analog
Output).
• Comparator based Analog Input Acquisition. Analog-to-digital
conversion is accomplished via 4-channel single slope ADC.
Digital I/O
• Eight bits of programmable digital I/O configurable as
interrupt sources.
THREE-PHASE PWM GENERATOR
The ADMC330 PWM controller is a self-contained program-
mable waveform generator that produces PWM switching sig-
nals for a three-phase power inverter. It includes a waveform
timing edge calculation unit which allows the generation of six
center based PWM signals based on only three duty cycle regis-
ter updates every switching cycle. This minimizes the DSP
software required to service the PWM controller and frees up
processor time for the motor control law implementation. In the
default configuration it produces the three-phase center based
PWM waveforms required for three phase sinusoidal inverter.
However, it can also be configured for space vector modulation
schemes, or for controlling brushless dc motors (sometimes
known as electronically commutated motors). It also has func-
tions which simplify the interface to the power inverter gate
drive and protection circuits.
The PWM controller is synchronized to the DSP core by the
HCLK which runs at half the DSP clock frequency giving wave-
form resolution of 100 ns with a 20 MHz DSP clock. There are
REV. 0
–5–
5 Page 
ADMC330
PWMDAC
R1 R2 R1 = R2 = 13k⍀
C1 = C2 = 10nF
C1 C2
Figure 7. Auxiliary PWM Output Filter
PROGRAMMABLE DIGITAL INPUT/OUTPUT
The ADMC330 has eight programmable digital I/O (PIO) pins:
PIO0–PIO7. Each pin can be individually configurable as either
an input or an output. Input pins can also be used to generate
interrupts.
The PIO pins are configured as input or output by setting the
appropriate bits in the PIODIR register, as shown in Figure 8.
The read/write register PIODATA is used to set the state of an
output pin or read the state of an input pin. Writing to PIODATA
affects only the pins configured as outputs. The default state,
after an ADMC330 reset, is that all PIO are configured as inputs.
Any pin can be configured as an independent edge triggered
interrupt source. The pin must first be configured as an input
and then the appropriate bit must be set in the PIOINTEN
register. A peripheral interrupt is generated when the input level
changes on any PIO pin configured as an interrupt source. A
PIO interrupt sets the appropriate bit in the PIOFLAG register.
The DSP peripheral interrupt service routine (ISR) must read
the PIOFLAG registers to determine which PIO pin was the
source of the PIO interrupt. Reading the PIOFLAG register will
clear it.
WATCHDOG TIMER OVERVIEW
The watchdog timer can be used to reset the DSP and peripher-
als in the event of a software error hanging the processor. The
watchdog timer is enabled by writing a value to the watchdog
timer register. In the event of the code “hanging” the counter
will count down from its initial value to zero and the watchdog
timer hardware will force a DSP and peripheral reset. In normal
operation a section of DSP code will write to the timer register
to reset the counter to its initial value preventing it from reach-
ing zero.
DSP CORE ARCHITECTURE OVERVIEW
Figure 9 is a block diagram of the ADMC330 processor core
and system peripherals. The processor contains three indepen-
dent computational units: The ALU, the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add and multiply/
subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormali-
zation and derive exponent operations. The shifter can be used to
efficiently implement numeric format control including multi-
word and block floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
PIODIR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 = OUTPUT
0 = INPUT
PIODATA
(READ/WRITE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 = HI
0 = LOW
PIOINTEN
(WRITE-ONLY)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 = ENABLE INTERRUPT
0 = DISABLE INTERRUPT
PIOFLAG
(READ-ONLY)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 = INTERRUPT FLAGGED
0 = NO INTERRUPT
PIO0
PIO7
Figure 8. Configuration of PIO Registers
REV. 0
–11–
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| PDF Descargar | [ Datasheet ADMC330BST.PDF ] | |
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