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ADMC326TN Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADMC326TN
Beschreibung 28-Lead ROM-Based DSP Motor Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADMC326TN Datasheet, Funktion
a
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives, Automotive
MOTOR TYPES
AC Induction Motors
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 24-Bit Program Memory RAM
4K ؋ 24-Bit Program Memory ROM
512 ؋ 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
28-Lead ROM-Based
DSP Motor Controller
ADMC326
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function
28-Lead SOIC or PDIP Package Options
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
4K ؋ 24
PROGRAM
RAM
512 ؋ 24
MEMORY
BLOCK
DATA
MEMORY
512 ؋ 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
VREF
6
ANALOG
INPUTS
16-BIT
3-PHASE
PWM
SERIAL PORT
SPORT1
9-BIT
PIO
2 ؋ 8-BIT
AUX
PWM
WATCH-
DOG
TIMER
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADMC326TN Datasheet, Funktion
ADMC326
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient)
ADMC326Y . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C
ADMC326T . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATION
PIO6/CLKOUT 1
28 PIO7/AUX1
PIO5/RFS1 2
27 PIO8/AUX0
PIO4/DR1A 3
26 AL
PIO3/SCLK1 4
25 AH
PIO2/DR1B 5
24 BL
PIO1/DT1 6
23 BH
ADMC326
PIO0/TFS1 7 TOP VIEW 22 CL
CLKIN 8 (Not to Scale) 21 CH
XTAL 9
20 RESET
VDD 10
PWMTRIP 11
19 GND
18 ICONST
V3 12
17 VAUX2
V2 13
16 VAUX1
V1 14
15 VAUX0
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN FUNCTION DESCRIPTIONS
Pin
Name
PIO6/CLKOUT
PIO5/RFS1
PIO4/DR1A
PIO3/SCLK1
PIO2/DR1B
PIO1/DT1
PIO0/TFS1
CLKIN
XTAL
VDD
PWMTRIP
V3
V2
V1
VAUX0
VAUX1
VAUX2
ICONST
GND
RESET
CH
CL
BH
BL
AH
AL
PIO8/AUX0
PIO7/AUX1
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
SUP
I
I
I
I
I
I
I
O
GND
I
O
O
O
O
O
O
I/O
I/O
ORDERING GUIDE
Model
Temperature
Range
Instruction
Rate
Package
Description
Package
Option
ADMC326YR-xxx-yy
ADMC326TR-xxx-yy
ADMC326YN-xxx-yy
ADMC326TN-xxx-yy
–40°C to +105°C
–40°C to +125°C
–40°C to +105°C
–40°C to +125°C
20 MHz
20 MHz
20 MHz
20 MHz
28-Lead Wide Body (SOIC)
28-Lead Wide Body (SOIC)
28-Lead Wide Body (PDIP)
28-Lead Wide Body (PDIP)
R-28
R-28
N-28
N-28
NOTES
xxx = customer identification code.
yy = ROM identification code.
To place an order for a custom ROM-coded ADMC326 processor, please request a copy of the ADMC ROM ordering package, available from your Analog Devices
Sales representative.
Analog Devices assesses a charge for each ROM mask generated in addition to a minimum order quantity. Please consult your sales representative for details.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC326 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. A

6 Page









ADMC326TN pdf, datenblatt
ADMC326
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
f PWM, min
=
20 × 106
2 × 65, 535
=
153
Hz
for a CLKOUT frequency of 20 MHz.
PWM Switching Dead Time: PWMDT Register
The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (for example
AH) and turning on its complementary signal, AL. This short
time delay is introduced to permit the power switch being turned
off to completely recover its blocking capability before the
complementary switch is turned on. This time delay prevents a
potentially destructive short-circuit condition from developing
across the dc link capacitor of a typical voltage source inverter.
Dead time is controlled by the PWMDT register. The dead
time is inserted into the three pairs of PWM output signals. The
dead time, TD, is related to the value in the PWMDT register by:
TD
=
PWMDT
× 2 × tCK
=
2 × PWMDT
fCLKOUT
Therefore, a PWMDT value of 0x00A (= 10), introduces a 1 µs
delay between the turn-off of any PWM signal (for example AH)
and the turn-on of its complementary signal (AL). The amount
of the dead time can therefore be programmed in increments of
2 tCK (or 100 ns for a 20 MHz CLKOUT). The PWMDT register
is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum
value of 0x3FF (= 1023) corresponds to a maximum programmed
dead time of:
TDmax = 1023 × 2 × tCK
= 1023 × 2 × 50 × 10–9 sec
= 102 µs
The dead time can be programmed to zero by writing 0 to the
PWMDT register.
PWM Operating Mode: MODECTRL and SYSSTAT Registers
The PWM controller of the ADMCF326 can operate in two dis-
tinct modes: single update mode and double update mode. The
operating mode of the PWM controller is determined by the
state of Bit 6 of the MODECTRL register. If this bit is cleared, the
PWM operates in the single update mode. Setting Bit 6 places
the PWM in the double update mode. By default, following
either a peripheral reset or power-on, Bit 6 of the MODECTRL
register is cleared. This means that the default operating mode
is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks
the start of a new PWM cycle and is used to latch new values
from the PWM configuration registers (PWMTM, PWMDT,
PWMPD and PWMSYNCWT) and the PWM duty cycle
registers (PWMCHA, PWMCHB and PWMCHC) into the
three-phase timing unit. The PWMSEG register is also latched
into the output control unit on the rising edge of the PWMSYNC
pulse. In effect, this means that the parameters of the PWM
signals can be updated only once per PWM period at the start of
each cycle. Thus, the generated PWM patterns are symmetrical
about the midpoint of the switching period.
In double update mode, there is an additional PWMSYNC pulse
produced at the midpoint of each PWM period. The rising edge
of this new PWMSYNC pulse is again used to latch new values
of the PWM configuration registers, duty cycle registers and the
PWMSEG register. As a result, it is possible to alter both the
characteristics (switching frequency, dead time, minimum pulse-
width and PWMSYNC pulsewidth) and the output duty cycles
at the midpoint of each PWM cycle. Consequently, it is pos-
sible to produce PWM switching patterns that are no longer
symmetrical about the midpoint of the period (asymmetrical
PWM patterns).
In the double update mode, operation in the first half or the
second half of the PWM cycle is indicated by Bit 3 of the
SYSSTAT register. In double update mode, this bit is cleared
during operation in the first half of each PWM period (between
the rising edge of the original PWMSYNC pulse and the rising
edge of the new PWMSYNC pulse, which is introduced in
double update mode). Bit 3 of the SYSSTAT register is set
during the second half of each PWM period. If required, a user
may determine the status of this bit during a PWMSYNC inter-
rupt service routine.
The advantages of the double update mode are that lower har-
monic voltages can be produced by the PWM process and wider
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the double
update mode.
Width of the PWMSYNC Pulse: PWMSYNCWT Register
The PWM controller of the ADMCF326 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM frequency
in the double update mode. This PWMSYNC synchronizes
the operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT register. The width of the PWMSYNC pulse,
TPWMSYNC, is given by:
( )TPWMSYNC = tCK × PWMSYNCWT + 1
which means that the width of the pulse is programmable from tCK
to 256 tCK (corresponding to 50 ns to 12.8 µs for a CLKOUT rate
of 20 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is 2.0 µs.
PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers
The duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA controls
the duty cycle of the signals on AH and AL. PWMCHB controls
the duty cycle of the signals on BH and BL, and PWMCHC
controls the duty cycle of the signals on CH and CL. The duty
cycle registers are programmed in integer counts of the funda-
mental time unit, tCK, and define the desired on-time of the
high-side PWM signal produced by the three-phase timing unit
over half the PWM period. The switching signals produced by
the three-phase timing unit are also adjusted to incorporate the
programmed dead time value in the PWMDT register.
–12–
REV. A

12 Page





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