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ADMC300-ADVEVALKIT Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADMC300-ADVEVALKIT
Beschreibung High Performance DSP-Based Motor Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADMC300-ADVEVALKIT Datasheet, Funktion
a
High Performance DSP-Based
Motor Controller
ADMC300
TARGET APPLICATIONS
Industrial Drives, Servo Drives, Variable Speed Drives,
Electric Vehicles
FEATURES
25 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (40 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
4K ؋ 24-Bit Program Memory RAM
2K ؋ 24-Bit Program Memory ROM
1K ؋ 16-Bit Data Memory RAM
High-Resolution Multichannel ADC System
Five Independent 16-Bit Sigma-Delta ADCs
76 dB SNR Typical (ENOB > 12 Bits)
Arranged in Two Independently Clocked Banks
Differential or Single-Ended Inputs
Programmable Sample Frequency to 32.5 kHz
Flexible Synchronization of ADC and PWM Subsystems
Independent Offset Calibration for Each Channel
Two Dedicated ADC Interrupts
Internal 2.5 V Reference
Three Multiplexer Control Pins for External Expansion
Hardware or Software Convert Start
Individual Power-Down for Each Bank
Three-Phase PWM Generation Subsystem
16-Bit Dedicated PWM Generator
Edge Resolution to 40 ns
Programmable Dead Time
Programmable Minimum Pulsewidth
Double Update Mode Allows Duty Cycle
Adjustment on Half Cycle Boundaries
Special Features for Brushless DC Motors
Hardwired Polarity Control
External Dedicated Asynchronous Shutdown Pin
(PWMTRIP)
Additional Shutdown Pins in I/O System
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Transparent Transition to Overmodulation
Range with Duty Cycles of 100%
Programmable Interrupt Controller Manages Priority
and Masking of 11 Peripheral Interrupts
(Continued on Page 7)
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
2K ؋ 24
PROGRAM
RAM
4K ؋ 24
MEMORY
DATA
RAM
1K ؋ 16
MOTOR CONTROL
PERIPHERALS
3
2 12
WATCH-
DOG
TIMER
PROGRAM
INTERRUPT
CONTROLLER
ENCODER
INTERFACE
EVENT
CAPTURE
TIMERS
DIGITAL
I/O
PROGRAM MEMORY ADDRESS BUS
DATA MEMORY ADDRESS BUS
PROGRAM MEMORY DATA BUS
DATA MEMORY DATA BUS
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
56
INTERVAL
TIMER
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AUXILIARY
PWM
SIGMA-DELTA
ADCs
PWM
GENERATION
2 10
7
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADMC300-ADVEVALKIT Datasheet, Funktion
ADMC300
Pin Pin
No. Type
1 GND
2I
3O
4 I/O
5 I/O
6 I/O
7 SUP
8 GND
9I
10 O
11 O
12 O
13 O
14 GND
15 SUP
16 O
17 O
18 O
19 O
20 O
PIN FUNCTION DESCRIPTIONS
Pin
Name
GND
DR0
DT0
RFS0
TFS0
SCLK0
VDD
GND
PWMTRIP
PWMSYNC
CL
CH
BL
GND
VDD
BH
AL
AH
MUX0
MUX1
Pin Pin
No. Type
21 O
22 GND
23 SUP
24 O
25 O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 GND
32 SUP
33 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 GND
Pin
Name
MUX2
GND
VDD
AUX0
AUX1
PIO0
PIO1
PIO2
PIO3
PIO4
GND
VDD
PIO5
PIO6
PIO7
PIO8
PIO9/CONVST
PIO10/ETU0
PIO11/ETU1
AGND
Pin Pin
No. Type
41 SUP
42 I
43 I
44 I
45 I
46 I
47 I
48 SUP
49 GND
50 GND
51 SUP
52 I
53 I
54 O
55 I
56 I
57 I
58 I
59 SUP
60 GND
Pin
Name
AVDD
V5N
V5
V4N
V4
V3N
V3
AVDD
AGND
AGND
AVDD
REFINB
REFINA
VREF
V2N
V2
V1N
V1
AVDD
AGND
Pin Pin
No. Type
61 GND
62 GND
63 I
64 I
65 I
66 I
67 I
68 GND
69 I
70 O
71 O
72 GND
73 SUP
74 I
75 I
76 O
77 I/O
78 I/O
79 I/O
80 SUP
Pin
Name
GND
GND
EIZP
EIA
EIB
RESET
PWMPOL
GND
CLKIN
XTAL
CLKOUT
GND
VDD
DR1A
DR1B
DT1
RFS1/SROM
TFS1
SCLK1
VDD
PIN CONFIGURATION
80-Lead Plastic Thin Quad Flatpack (TQFP)
(ST-80)
GND 61
GND 62
EIZP 63
EIA 64
EIB 65
RESET 66
PWMPOL 67
GND 68
CLKIN 69
XTAL 70
CLKOUT
GND
VDD
DR1A
DR1B
DT1
RFS1/ SROM
TFS1
SCLK1
VDD
71
72
73
74
75
76
77
78
79
80
PIN 1
IDENTIFIER
ADMC300
TOP VIEW
(Not to Scale)
40 AGND
39 PIO11/ETU1
38 PIO10/ETU0
37 PIO9/CONVST
36 PIO8
35 PIO7
34 PIO6
33 PIO5
32 VDD
31 GND
30 PIO4
29 PIO3
28 PIO2
27 PIO1
26 PIO0
25 AUX1
24 AUX0
23 VDD
22 GND
21 MUX2
–6– REV. B

6 Page









ADMC300-ADVEVALKIT pdf, datenblatt
ADMC300
program and data memory RAM can be loaded from the SROM/
E2PROM. After the boot load is complete, program execution
begins at address 0x0060. This is where the first instruction of
the user code should be placed.
If boot loading from an E2PROM is unsuccessful, the monitor
code reconfigures SPORT1 as a UART and attempts to receive
commands from an external device on this serial port. The
monitor then waits for a byte to be received over SPORT1,
locks onto the baud rate of the external device (autobaud fea-
ture) and takes in a header word that tells it with what type of
device it is communicating. There are six alternatives:
A UART boot loader such as a Motorola 68HC11 SCI port.
A synchronous slave boot loader (the clock is external).
A synchronous master boot loader (the ADMC300 provides
the clock).
A UART debugger interface.
A synchronous master debugger interface.
A synchronous slave debugger interface.
With the debugger interface, the monitor enters interactive
mode in which it processes commands received from the
external device.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is
set, disabled when this bit is cleared. SPORT1 is enabled when
Bit 11 is set, disabled when this bit is cleared. SPORT1 is con-
figured as a serial port when Bit 10 is set, or as flags and inter-
rupt lines when this bit is cleared. For proper operation of the
ADMC300, all other bits in this register must be cleared (which
is their default).
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). For proper operation of the
ADMC300, this register must always contain the value 0x8000
(which is the default).
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC300 is shown at the end of the data sheet.
ANALOG-TO-DIGITAL CONVERSION SYSTEM
A functional block diagram of the ADC system of the ADMC300
is shown in Figure 5. The ADC system provides the high perfor-
mance conversion required for precision applications. It integrates
five completely independent analog-to-digital converters based
on sigma-delta conversion technology. Each ADC channel may
REFINA
REFINB
V1
V1N
V2
V2N
V3
V3N
V4
V4N
CALIBRATION
MULTIPLEXER
ADC BANKA
16-BIT ⌺⌬
ADC1 (15…0)
16-BIT ⌺⌬
16-BIT ⌺⌬
16-BIT ⌺⌬
ADC2 (15…0)
ADC3 (15…0)
ADC4 (15…0)
DSP DATA
MEMORY
BUS
V5
V5N
16-BIT ⌺⌬
ADC5 (15…0)
ADC BANKB
ADCCAL (4…0)
CONVST(PIO9)
UPDATE
ADC REGISTER
UPDATE CONTROL
ADCDIVA (11…6)
ADCDIVB (11…6)
ADCSYNC (6…0)
MUX0
MUX1
MUX2
MULTIPLEXER
CONTROL
ADCCTRL (15…0)
INTERNAL
VOLTAGE
REFERENCE
GENERATOR
Figure 5. Functional Block Diagram of ADC System of ADMC300
VREF
–12–
REV. B

12 Page





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