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ADMC201AP Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADMC201AP
Beschreibung Motion Coprocessor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 15 Seiten
ADMC201AP Datasheet, Funktion
a
Motion Coprocessor
ADMC201
FEATURES
Analog Input Block
11-Bit Resolution Analog-to-Digital (A/D) Converter
7 Single-Ended (SE) Analog Inputs
4 Simultaneously Sampled Analog Inputs
Expansion with 4 Multiplexed Inputs
3.2 s Conversion Time/Channel
0 V–5 V Analog Input Range
Internal 2.5 V Reference
PWM Synchronized Sampling Capability
12-Bit PWM Timer Block
Three-Phase Center-Based PWM
1.5 kHz–25 kHz PWM Switching Frequency Range
Programmable Deadtime
Programmable Pulse Deletion
PWM Synchronized Output
External PWM Shutdown
Vector Transformation Block
12-Bit Vector Transformations
Forward and Reverse Clarke Transformations
Forward and Reverse Park Rotations
2.9 s Transformation Time
Programmable Digital I/O Port
6-Bit Configurable Digital I/O
Change of State Interrupt Support
DSP & Microcontroller Interface
12 Bit Memory Mapped Registers
Twos Complement Data Format
6.25 MHz to 25 MHz Operating Clock Range
68-Pin PLCC Package
Single 5 V DC Power Supply
Industrial Temperature Range
GENERAL DESCRIPTION
The ADMC201 is a motion coprocessor that can be used with
either microcontrollers or digital signal processors (DSP). It
provides the functionality that is required to implement a digital
control system. In a typical application, the DSP or micro-
controller performs the control algorithms (position, speed,
torque and flux loops) and the ADMC201 provides the neces-
sary motor control functions: analog current data acquisition,
vector transformation, digital inputs/outputs, and PWM drive
signals.
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs
A four channel sample and hold amplifier allows three-phase
motor currents to be sampled simultaneously, reducing errors
from phase coherency. Sample and hold acquisition time is
1.6 µs and conversion time per channel is 3.2 µs (using a 12.5 MHz
system clock).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
RESET
WR
A0–3
RD
CS
IRQ
CLK
REFOUT
REFIN
CONVST
U
V
W
AUX
AUX0
AUX1
AUX2
AUX3
PWMSYNC
A
AP
B
BP
C
CP
STOP
FUNCTIONAL BLOCK DIAGRAM
D0–D11
DATABUS
EMBEDDED
CONTROL
SEQUENCER
CONTROL BUS
INTERNAL
REFERENCE
CONTROL
REGISTERS
11-BIT
A/D
CONVERTER
MULTIPLEXER
EXPANSION
BLOCK
12-BIT
PWM TIMER
BLOCK
VECTOR
TRANSFORMATION
BLOCK
PROG.
DIGITAL
I/O
PORT
PIO 0–5
Flexible Analog Channel Sequencing
The ADMC201 supports acquisition of 2, 3, or 4 channels per
group. Converted channel results are stored in registers and
the data can be read in any order. The sampling and conversion
time for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).
Embedded Control Sequencer
The embedded control sequencer off-loads the DSP or micro-
processor, reducing the instructions required to read analog
input channels, control PWM timers and perform vector trans-
formations. This frees the host processor for performing control
algorithms.
Fast DSP/Microprocessor Interface
The high speed digital interface allows direct connection to 16-bit
digital signal processors and microprocessors. The ADMC201
has 12 bit memory mapped registers with twos complement
data format and can be mapped directly into the data memory
map of a DSP. This allows for a single instruction read and write
interface.
Integration
The ADMC201 integrates a four channel simultaneous sampling
analog-to-digital converter, four channel analog multiplexer,
analog reference, vector transformation, six digital inputs/outputs,
and three-phase PWM timers into a 68-pin PLCC. Integration
reduces cost, board space, power consumption, and design and
test time.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADMC201AP Datasheet, Funktion
ADMC201
ANALOG INPUT BLOCK
The ADMC201 contains an 11-bit resolution, successive approxi-
mation analog-to-digital (A/D) converter with twos complement
output data format. The analog input range is ± 2.5 V (0 V–5 V)
with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V ±
5% reference is utilized by connecting the REFOUT pin to the
REFIN pin.
The input stage to the A/D converter is a four channel SHA
which allows the four channels (U, V, W and AUX) to be held
simultaneously and then sequentially digitized. The auxiliary
input (AUX) is fed by a four channel multiplexer that allows the
channels AUX0, AUX1, AUX2 and AUX3 to be individually
converted along with the primary channels U, V and W. The
auxiliary inputs are ideal for reading slower changing variables
such as bus voltage and temperature. The A/D conversion time
is determined by the system clock frequency, which can range
from 6.25 MHz to 12.5 MHz. The Sample and Hold (SHA)
acquisition time is 20 system clock cycles and is independent of
the number of channels sampled and/or digitized. Forty system
clock cycles are required to complete each A/D conversion. The
analog channel sampling is flexible and is programmable
through the SYSCTRL register. The minimum number of
channels per conversion is two. The throughput time of the
analog acquisition block can be calculated as follows:
tAA = tSHA + (n × tCONV )
where
tAA = analog acquisition time,
n = # channels,
tSHA = SHA acquisition time (20 × system clock period),
tCONV = conversion time (40 × system clock period) per channel.
A/D Conversions are initiated via the CONVST pin. A syn-
chronizing pulse (PWMSYNC) is provided at the beginning of
each PWM cycle. This pulse can be used to synchronize the
A/D conversion process to the PWM switching frequency.
Operating the A/D Converter
The A/D converter can be set up to convert a sequence of channels
as defined in the SYSCTRL register (see Table VI). The default
channel select mode after RESET is to convert channels V and
W only. This is two-/three-phase mode. Three-/three-phase
mode converts channels U, V, W, and/or AUX. Three-/three-
phase mode is selected by writing a 1 to Bit 3 of the SYSCTRL
register. After the conversion process is complete, the channels
can be read in any order.
There are two methods that can be used to indicate when the
A/D conversions are completed and the data is ready: interrupt
driven and software timing.
Interrupt Driven Method
Interrupts can be used to indicate the end of conversion for a
group of channels. Before beginning any A/D conversions, Bit 7
of the SYSCTRL register must be set to 1 to enable A/D con-
version interrupts. Then, when an A/D conversion is complete,
an interrupt will be generated. After an interrupt is detected,
Bit 0 of the SYSSTAT register must be checked to determine if
the A/D converter was the source. Reading the SYSSTAT reg-
ister automatically clears the interrupt flag bits.
Software Timing Method
An alternative method is to use the DSP or microcontroller to
keep track of the amount of time elapsed between CONVST
and the expected completion time (n × tCONV).
Reading Results
The 11-bit A/D conversion results for channels U, V, W and
AUX are stored in the ADCU, ADCV, ADCW and ADCAUX
registers respectively. The twos complement data is left justified
and the LSB is set to zero. The relationship between input volt-
age and output coding is shown in Figure 5.
OUTPUT
CODE
FULL-SCALE
TRANSITION
01 1 1 1 1 1 1 1 1 1 0
000000000000
FS = 5V
LSB = 5V
2048
100000000000
0V
2.5 5V1LSB
INPUT VOLTAGE
Figure 5. Transfer Function
Sample and Hold
After powering up the ADMC201, bring the RESET pin low for
a minimum of two clock cycles in order to enable A/D conversions.
Before initiating the first conversion (CONVST) after a reset,
the SHA time of 20 system clock cycles must occur. A conversion
is initiated by bringing CONVST high for a minimum of one
system clock cycle. The SHA goes into hold mode at the falling
edge of clock.
Following completion of the A/D conversion process, a minimum
of 20 system clock cycles are required before initiating another
conversion in order to allow the sample and hold circuitry to
reacquire the input signals.
If a CONVST is initiated before the 20 clock cycles have elapsed,
the embedded control sequencer will delay conversion until this
requirement is met.
6REV. B

6 Page









ADMC201AP pdf, datenblatt
ADMC201
Name
RHO
PHIP1/VD
PHIP2/VQ
PHIP3
RHOP
PWMTM
PWMCHA
PWMCHB
PWMCHC
PWMDT
PWMPD
PIOCTRL
PIODATA
SYSCTRL
Name
ID/PHV1/VX
IQ/PHV2
IX/PHV3
IY/VY
ADCV
ADCW
ADCAUX
ADCU
PIODATA
SYSCTRL
SYSSTAT
Table III. Write Registers
A3 A2 A1 A0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Register Function
Load RHO (ρ) and Start Reverse Transform
Reverse Rotation Direct Input/Forward Direct Input
Reverse Rotation Direct Input/Forward Direct Input
Reverse Rotation Direct Input
Load RHOP (ρ) and Start Forward Transform
PWM Master Switching Period
PWM Channel A On-Time
PWM Channel B On-Time
PWM Channel C On-Time
PWM Programmable Deadtime (7-Bit Register)
PWM Pulse Deletion Value (7-Bit Register)
Digital I/O Control
Digital I/O Data Write (6-Bit Register)
System Control
Reserved
Reserved
Table IV. Read Registers
A3 A2 A1 A0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Register Function
Reverse Rotation Result (IDS)/Forward Result Cos +0°
Reverse Rotation Result (IQS)/Forward Cos +120°
Reverse Clarke Cos +0°/Forward Result Cos +240°
Reverse Clarke Cos +90°/Forward Cos +90°
Reserved
A/D Conversion Result Channel V
A/D Conversion Result Channel W
A/D Conversion Result Auxiliary Channel
A/D Conversion Result Channel U
Reserved
Reserved
Reserved
Digital I/O Data Read (6-Bit Register)
System Control
System Status
Reserved
12REV. B

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