PDF ADMC201 Data sheet ( Hoja de datos )

Número de pieza	ADMC201
Descripción	Motion Coprocessor
Fabricantes	Analog Devices
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No Preview Available ! a Motion Coprocessor ADMC201 FEATURES Analog Input Block 11-Bit Resolution Analog-to-Digital (A/D) Converter 7 Single-Ended (SE) Analog Inputs 4 Simultaneously Sampled Analog Inputs Expansion with 4 Multiplexed Inputs 3.2 ␮s Conversion Time/Channel 0 V–5 V Analog Input Range Internal 2.5 V Reference PWM Synchronized Sampling Capability 12-Bit PWM Timer Block Three-Phase Center-Based PWM 1.5 kHz–25 kHz PWM Switching Frequency Range Programmable Deadtime Programmable Pulse Deletion PWM Synchronized Output External PWM Shutdown Vector Transformation Block 12-Bit Vector Transformations Forward and Reverse Clarke Transformations Forward and Reverse Park Rotations 2.9 ␮s Transformation Time Programmable Digital I/O Port 6-Bit Configurable Digital I/O Change of State Interrupt Support DSP & Microcontroller Interface 12 Bit Memory Mapped Registers Twos Complement Data Format 6.25 MHz to 25 MHz Operating Clock Range 68-Pin PLCC Package Single 5 V DC Power Supply Industrial Temperature Range GENERAL DESCRIPTION The ADMC201 is a motion coprocessor that can be used with either microcontrollers or digital signal processors (DSP). It provides the functionality that is required to implement a digital control system. In a typical application, the DSP or micro- controller performs the control algorithms (position, speed, torque and flux loops) and the ADMC201 provides the neces- sary motor control functions: analog current data acquisition, vector transformation, digital inputs/outputs, and PWM drive signals. PRODUCT HIGHLIGHTS Simultaneous Sampling of Four Inputs A four channel sample and hold amplifier allows three-phase motor currents to be sampled simultaneously, reducing errors from phase coherency. Sample and hold acquisition time is 1.6 µs and conversion time per channel is 3.2 µs (using a 12.5 MHz system clock). REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. RESET WR A0–3 RD CS IRQ CLK REFOUT REFIN CONVST U V W AUX AUX0 AUX1 AUX2 AUX3 PWMSYNC A AP B BP C CP STOP FUNCTIONAL BLOCK DIAGRAM D0–D11 DATABUS EMBEDDED CONTROL SEQUENCER CONTROL BUS INTERNAL REFERENCE CONTROL REGISTERS 11-BIT A/D CONVERTER MULTIPLEXER EXPANSION BLOCK 12-BIT PWM TIMER BLOCK VECTOR TRANSFORMATION BLOCK PROG. DIGITAL I/O PORT PIO 0–5 Flexible Analog Channel Sequencing The ADMC201 supports acquisition of 2, 3, or 4 channels per group. Converted channel results are stored in registers and the data can be read in any order. The sampling and conversion time for two channels is 8 µs, three channels is 11.2 µs, and four channels is 14.4 µs (using a 12.5 MHz system clock). Embedded Control Sequencer The embedded control sequencer off-loads the DSP or micro- processor, reducing the instructions required to read analog input channels, control PWM timers and perform vector trans- formations. This frees the host processor for performing control algorithms. Fast DSP/Microprocessor Interface The high speed digital interface allows direct connection to 16-bit digital signal processors and microprocessors. The ADMC201 has 12 bit memory mapped registers with twos complement data format and can be mapped directly into the data memory map of a DSP. This allows for a single instruction read and write interface. Integration The ADMC201 integrates a four channel simultaneous sampling analog-to-digital converter, four channel analog multiplexer, analog reference, vector transformation, six digital inputs/outputs, and three-phase PWM timers into a 68-pin PLCC. Integration reduces cost, board space, power consumption, and design and test time. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page ADMC201 Pin Mnemonic Type 1 D9 2 D10 3 D11 4 PIO0 5 PIO1 6 PIO2 7 PIO3 8 PIO4 9 PIO5 10 VDD 11 A3 12 A2 13 A1 14 A0 15 NC 16 RESET BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR SUP I/P I/P I/P I/P I/P 17 CONVST I/P 18 IRQ O/P 19 VDD 20 DGND SUP GND 21 CLK 22 WR 23 RD 24 CS I/P I/P I/P I/P 25 NC 26 VDD 27 AGND SUP GND 28 AGND GND 29 U I/P 30 V I/P 31 W I/P 32 SGND GND 33 REFIN I/P 34 AUX3 I/P 35 AUX2 I/P 36 AUX1 I/P 37 AUX0 I/P PIN DESIGNATIONS Description Data Bit 9 Data Bit 10 Data Bit 11, MSB Programmable Digital I/O Bit 0 Programmable Digital I/O Bit 1 Programmable Digital I/O Bit 2 Programmable Digital I/O Bit 3 Programmable Digital I/O Bit 4 Programmable Digital I/O Bit 5 +5 V Digital Power Supply Address Bit 3, MSB Address Bit 2 Address Bit 1 Address Bit 0, LSB No Connect Chip Reset A/D Conversion Start Interrupt Request (Pull-Up Required) +5 V Digital Power Supply Digital Ground External Clock Input Write Select Output Enable/Read Chip Select No Connect +5 V Analog Power Supply Analog Ground Analog Ground Analog Input U Analog Input V Analog Input W Analog Signal Ground Analog Reference Input Auxiliary Analog Input 3 Auxiliary Analog Input 2 Auxiliary Analog Input 1 Auxiliary Analog Input 0 Pin Mnemonic Type 38 REFOUT O/P 39 VDD 40 DGND SUP GND 41 DGND GND 42 DGND GND 43 DGND GND 44 VDD 45 NC SUP 46 DGND GND 47 STOP I/P 48 PWMSYNC O/P 49 CP O/P 50 C O/P 51 BP O/P 52 NC 53 B O/P 54 AP O/P 55 A O/P 56 DGND GND 57 DGND GND 58 DGND GND 59 VDD 60 D0 SUP BIDIR 61 D1 BIDIR 62 D2 BIDIR 63 D3 BIDIR 64 D4 BIDIR 65 D5 BIDIR 66 D6 BIDIR 67 D7 BIDIR 68 D8 BIDIR Description Internal 2.5 V Analog Reference +5 V Digital Power Supply Digital Ground Digital Ground Digital Ground Digital Ground +5 V Digital Power Supply No Connect Digital Ground PWM Timer Output Disable PWM Synchronization Output PWM Timer Output C Prime PWM Timer Output C PWM Timer Output B Prime No Connect PWM Timer Output B PWM Timer Output A Prime PWM Timer Output A Digital Ground Digital Ground Digital Ground +5 V Digital Power Supply Data Bit 0, LSB Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 Pin Types I/P = Input Pin O/P = Output Pin GND = Ground Pin Pin Types BIDIR = Bidirectional Pin SUP = Supply Pin PIN CONFIGURATION 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VDD 10 A3 11 A2 12 A1 13 A0 14 NC 15 RESET 16 CONVST 17 IRQ 18 VDD 19 DGND 20 CLK 21 WR 22 RD 23 CS 24 NC 25 VDD 26 PIN 1 IDENTIFIER ADMC201 TOP VIEW (Not to Scale) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 60 D0 59 VDD 58 DGND 57 DGND 56 DGND 55 A 54 AP 53 B 52 NC 51 BP 50 C 49 CP 48 PWMSYNC 47 STOP 46 DGND 45 NC 44 VDD NC = NO CONNECT REV. B –5– 5 Page A0–A15 TMS320C20 TMS320C25 TMS320C25-50 IS INTn STRB R/W ADDRESS BUS VDD ADDRESS DECODE EN A0–A3 CS IRQ ADMC201 RD WR CLKOUT1 D0–D15 CLK D0–D11 DATA BUS Figure 12. TI Second Generation Devices TMS320C20/ C25/C25–50 In the case of the ADSP-2171/2181, the system clock is inter- nally scaled, a 10 MHz system clock will derive a 20 MHz CLKOUT. In the case of the TMS320C2X, the CLKOUT1 signal is derived from the system clock divided by a factor of 4, consequently a 50 MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for use by the ADMC201. Note: a pull-up resistor is required on the IRQ (Pin 18) output from the ADMC201. The STOP (Pin 47) must be tied low if not in use. ADMC201 REGISTER ADDRESSING Four address lines (A0 through A3) are used in conjunction with the control lines (CS, WR, RD,) to select registers 0 through 15. The CS and RD control lines are active low. The registers are given symbolic names. Table II. Pin Function CS Enables the ADMC201 register interface (connect via chip select logic-active low) RD Places data from the internal register onto the data bus WR Loads the internal register with data on the data bus on its positive edge DESCRIPTION OF THE REGISTERS All unspecified register locations are reserved. SYSCTRL System Control Register (See Tables V, VI, VII). SYSSTAT System Status Register (See Table VII). ADCU ADCV These registers contain the results from the first three analog input channels ADCW U, V, and W. The output data format is twos complement and, therefore, Bit 0 is always zero as the A/D converter has 11-bit resolution. ADCAUX This register contains the conversion result of the auxiliary channels AUX0, AUX1, AUX2 or AUX3. PWMTM PWM Master Switching Period PWMCHA PWM Channel A On-Time PWMCHB PWM Channel B On-Time PWMCHC PWM Channel C On-Time PWMDT PWM Programmable Deadtime Value PWMPD PWM Programmable Pulse Deletion Value ID/IQ These are the results of the reverse rotation (torque and flux components). PHV1/2/3 These are the results from the forward Clarke Transformation. PHIP1/2/3 IX/IY VX, VY RHOP RHO PIODATA PIOCTRL The inputs for reverse vector transforma- tion (Clarke and Park). These registers contain the results of the Clarke transformation that are the inputs to the reverse Park rotation. VX, VY contain the results of the forward Park rotation. RHOP is the angle used during the forward vector transformation. Writing to the RHOP register causes the forward rotation to start based on values in RHOP, VD and VQ registers. RHO is the angle used during the reverse vector transformation. Writing to this register starts the reverse rotation using the values in the RHO, PHIP1/2/3 registers. RHO and RHOP are unsigned ratios of 360°. For example, 45 degrees would be 45/360 × 212. Write to this register to change the digital outputs and read from it to determine the state of digital inputs. This register is used to configure the digital I/O as input or output and to enable interrupt on change of state. REV. B –11– 11 Page

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