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PDF ADM9690 Data sheet ( Hoja de datos )
| Número de pieza | ADM9690 | |
| Descripción | Power Supply and Watchdog Timer Monitoring Circuit | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Precision Voltage Monitor (4.31 V)
Watchdog Timeout Monitor
Selectable Watchdog Timeout—0.75 ms, 1.5 ms,
12.5 ms, 25 ms
Two RESET Outputs
APPLICATIONS
Microprocessor Systems
Computers
Printers
Controllers
Intelligent Instruments
Power Supply and Watchdog Timer
Monitoring Circuit
ADM9690
FUNCTIONAL BLOCK DIAGRAM
VCC
VMON
4.31V
ADM9690
OSC SEL1
OSC SEL2
WATCHDOG
TIMEBASE
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
RESET(1)
TIMER
RESET(2)
TIMER
GND
RESET(1)
RESET(2)
GENERAL DESCRIPTION
The ADM9690 contains a voltage monitoring comparator and a
watchdog timer monitor. It is designed to monitor the 5 V
power supply to a microprocessor and the microprocessor opera-
tion via a watchdog function.
The voltage monitoring comparator monitors the voltage on
VMON. If it drops outside tolerance, as will happen during a
power-fail, two reset signals are generated. Both reset signals go
active (low) simultaneously. They will remain active while
VMON is below the threshold, and for 50 ms (RESET(1)) or
60 ms (RESET(2)) after VMON climbs above the reset thresh-
old. RESET(1) is intended to provide a power-on reset signal
for the µP while RESET(2) is used to hold additional circuitry
in a reset state until the µP has regained control following a
power-up. The voltage monitoring circuitry remains operational
with VCC as low as 2 V.
The watchdog timer monitoring circuit is designed to monitor
the activity on the WDI input. This input is normally connected
to an output line on the µP. Its function is to check that the
microprocessor has not stalled in an infinite loop. If there is a
period of inactivity for the watchdog timeout period, both reset
outputs are activated. As above, RESET(1) remains low for
50 ms while RESET(2) remains low for an additional 10 ms.
The watchdog timer is restarted when RESET(1) goes inactive.
The actual watchdog timeout period is adjustable using two
select inputs SEL1 and SEL2.
The ADM9690 is available in an 8-lead SOIC package. It is
specified over the industrial temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
POWER SUPPLY AND WATCHDOG MONITORING
CIRCUIT
The ADM9690 contains a power supply voltage monitoring
comparator and a watchdog timer monitor. Either VMON drop-
ping outside tolerance or the watchdog timer timing out results
in a reset sequence as discussed below. Two reset outputs are
provided. RESET(1) and RESET(2).
POWER FAIL/POWER-ON RESET
When VMON falls below the reset threshold (4.4 V) both RESET
outputs are forced low immediately.
On power-up, RESET(1) will remain low for 50 milliseconds
after VMON rises above the reset threshold. This provides a
power-on reset for the microprocessor. RESET(2) remains
active low for an additional 10 ms. RESET(1) is intended to
VCC
VMON
4.31V
OSC SEL1
OSC SEL2
WATCHDOG
TIMEBASE
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
ADM9690
RESET(1)
TIMER
RESET(2)
TIMER
RESET(1)
RESET(2)
GND
Figure 6. Functional Block Diagram
ADM9690
provide a power-on reset signal for the µP while RESET(2) is
used to hold additional circuitry in a reset state until the µP has
regained control following a power-up.
The guaranteed minimum and maximum thresholds for the
ADM9690 are 4.3 V and 4.5 V.
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an infinite
loop. An output line on the processor may be used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, both RESET outputs are taken active
(low). RESET(1) remains low for 50 ms and RESET(2) re-
mains low for an additional 10 ms . Each transition (either
positive-going or negative-going) of WDI after RESET(1) has
gone inactive restarts the watchdog timer. The actual watchdog
timeout period is adjustable using SEL1 and SEL2. Four timeout
periods are selectable. Please refer to Table I.
The watchdog timer is restarted at the end of RESET(1)
(RESET(1) going high), whether the reset was caused by lack of
activity on WDI or by VMON falling below the reset threshold.
Table I.
SEL2
0
0
1
1
SEL1
0
1
0
1
Watchdog Timeout
Period tWD (ms)
0.75
1.5
12.5
25
VMON
RESET(1)
RESET(2)
t1
t2
Figure 7. Power-On RESET Timing
WDI
RESET(1)
RESET(2)
tWD
t1
t2
Figure 8. Watchdog RESET Timing
REV. A
–5–
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ADM9690.PDF ] | |
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