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ADM694 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM694
Beschreibung Microprocessor Supervisory Circuits
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADM694 Datasheet, Funktion
a
Microprocessor
Supervisory Circuits
ADM690–ADM695
FEATURES
Superior Upgrade for MAX690–MAX695
Specified Over Temperature
Low Power Consumption (5 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V VCC
Low Switch On-Resistance 1.5 Normal,
20 in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
600 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (5 ns)
Voltage Monitor for Power Fail
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
GENERAL DESCRIPTION
The ADM690–ADM695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection, and power failure warn-
ing. The complete family provides a variety of configurations to
satisfy most microprocessor system requirements.
The ADM690, ADM692 and ADM694 are available in 8-pin
DIP packages and provide:
1. Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.3 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.
The ADM691, ADM693 and ADM695 are available in 16-pin
DIP and small outline packages and provide three additional
functions.
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
FUNCTIONAL BLOCK DIAGRAMS
VBATT
VOUT
VCC
4.65V 1
RESET
GENERATOR2
RESET
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
WATCHDOG
TRANSITION DETECTOR
(1.6s)
1.3V
ADM690
ADM692
ADM694
POWER FAIL
OUTPUT (PFO)
1VOLTAGE DETECTOR = 4.65V (ADM690, ADM694)
4.40V (ADM692)
2RESET PULSE WIDTH = 50ms (ADM690, ADM692)
200ms (ADM694)
BATT ON
VBATT
VCC
CEIN
4.65V 1
OSC IN
OSC SEL
RESET &
WATCHDOG
TIMEBASE
ADM691
ADM693
ADM695
VOUT
CEOUT
LOW LINE
RESET
GENERATOR
RESET
RESET
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
WATCHDOG
TRANSITION DETECTOR
1.3V
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
1VOLTAGE DETECTOR = 4.65V (ADM691, ADM695)
4.40V (ADM693)
The ADM690–ADM695 family is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(5 mW), extremely fast Chip Enable gating (5 ns) and high reli-
ability. RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for mini-
mal voltage drop thereby permitting increased output current
drive of up to 100 mA without the need for an external pass
transistor.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADM694 Datasheet, Funktion
ADM690–ADM695
POWER FAIL RESET OUTPUT
RESET is an active low output which provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690/
ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693).
VCC V2
V1 V2
V1
RESET
t1
t1
LOW LINE
t1 = RESET TIME.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power Fail Reset Timing
On power-up RESET will remain low for 50 ms (200 ms for
ADM694 and ADM695) after VCC rises above the appropriate
reset threshold. This allows time for the power supply and mi-
croprocessor to stabilize. On power-down, the RESET output
remains low with VCC as low as 1 V. This ensures that the
microprocessor is held in a stable shutdown condition.
This RESET active time is adjustable on the ADM691/ADM693/
ADM695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table I and
Figure 4.
The guaranteed minimum and maximum thresholds of the
ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V,
while the guaranteed thresholds of the ADM692/ADM693 are
4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695
is, therefore, compatible with 5 V supplies with a +10%, –5%
tolerance while the ADM692/ADM693 is compatible with 5 V
± 10% supplies. The reset threshold comparator has approxi-
mately 50 mV of hysteresis. The response time of the reset volt-
age comparator is less than 1 µs. If glitches are present on the
VCC line which could cause spurious reset pulses, then VCC
should be decoupled close to the device.
In addition to RESET the ADM691/ADM693/ADM695 con-
tain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
RESET signal.
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695
may be configured for either a fixed “short” 100 ms or a “long”
1.6 second timeout period or for an adjustable timeout period.
If the “short” period is selected, some systems may be unable to
service the watchdog timer immediately after a reset, so the
ADM691/ADM693/ADM695 automatically selects the “long”
timeout period directly after a reset is issued. The watchdog
timer is restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by VCC falling below the
reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” timeout period (1.6 s). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
WDI
WDO
RESET
t2 t3
t1 t1
t1
t1 = RESET TIME.
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
Figure 3. Watchdog Timeout Period and Reset Active
Time
–6– REV. A

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ADM694 pdf, datenblatt
ADM690–ADM695
R =(VCC – 50 mV)/1 µA
Note that the resistor will discharge the battery slightly. With a
VCC supply of 4.5 V, a suitable resistor is 4.3 M. With a 3 V
battery this will draw around 700 nA. This will be negligible in
most cases.
BATTERY
VBATT
R
ADM69x
+5V
R1
R2
+
BATTERY
VCC
VOUT
PFI
ADM690
ADM692
ADM694
VBATT
RESET
PFO
GND WDI
0.1µF
µP POWER
CMOS RAM
POWER
µP SYSTEM
µP RESET
µP NMI
I/O LINE
Figure 22b. Preventing Spurious RESETS During Battery
Replacement
TYPICAL APPLICATIONS
ADM690, ADM692 AND ADM694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. VOUT powers the
CMOS RAM. Under normal operating conditions with VCC
present, VOUT is internally connected to VCC. If a power failure
occurs, VCC will decay and VOUT will be switched to VBATT
thereby maintaining power for the CMOS RAM. A RESET
pulse is also generated when VCC falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692. RESET will
remain low for 50 ms (200 ms for ADM694) after VCC returns
to 5 V.
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT.
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) – 1
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. This gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
INPUT
POWER
V > 8V
R1
R2
BATTERY
7805
+5V
0.1µF
VCC
VOUT
PFI
ADM690
ADM692
ADM694
VBATT
RESET
PFO
GND WDI
0.1µF
µP POWER
CMOS RAM
POWER
µP SYSTEM
µP RESET
µP NMI
I/O LINE
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
ADM691, ADM693, ADM695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from VOUT. When
5 V power is present this is routed to VOUT. If VCC fails then
VBATT is routed to VOUT. VOUT can supply up to 100 mA from
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBATT, the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20 MOSFET connects the
backup battery to VOUT.
–12–
REV. A

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