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ADM6308 Schematic ( PDF Datasheet ) - ETC

Teilenummer ADM6308
Beschreibung Eight-port 10/100M Ethernet Switch Controller
Hersteller ETC
Logo ETC Logo 




Gesamt 17 Seiten
ADM6308 Datasheet, Funktion
ADMtek Incorporated
Olive Family
Partnership Now and Future
ADM6308 Eight-port 10/100M Ethernet Switch Controller
Overview
ADM6308, a single chip, is a 10/100Mbps eight-port stand-alone switching controller with built-in data buffer memory which
provides low cost and simple solution though a high integration design. Eight Reduced MII interfaces are designed for
10BASE/100BASE ports. MAC controller, switch engines and data buffer memory are built-in. The chip can fit to desktop or
SOHO applications, and each 10/100M port directly connects either 10BASE or 100BASE devices. Additionally, ADM6308
breaks the distance limitation of 10BASE or any class 100BASE repeaters, and increases throughput.
Features
ê Non-blocking eight-port 10/100M switching controller with MAC controller and switching engine included low cost and a
simple solution for 100BASE-TX, 100BASE-FX, and 10BASE applications.
ê Configurable 10/100BASE Reduced MII interfaces and 1MII+ 7RMII mode provided.
ê The single clock input, 50M, for RMII and system
ê Speed auto negotiation function for all ports
ê Store-and- forward operation support.
ê Full line speed capability of 14880 packet/sec for 10M and 148810 packet/sec for 100M, with no HOL blocking.
ê Broadcast storming prevention
ê Support 4 groups port-based VLAN.
ê Full-duplex (IEEE802.3x) and three-way half-duplex flow control (Back pressure).
ê Data buffer SSRAM embedded,
ê CoS support: Port-based, VLAN tag, TCP/IP TOS/DS.
ê Intelligently back-pressure and flow control turned on/off in the port with priority frames
ê Buffer management included.
ê 93C46 EEPROM interface or Dynamic configured by 8051
ê Buffer full and faulty LED provided.
ê Bridging functions such as:
u Local MAC address filtering.
u CRC or direct mapping hashing schemes for better address coverage.
u Short routing decision time.
u Aging function included with configurable aging time.
u Embedded 1K entries of address table.
ê Low power 2.5 V CMOS technology with 3.3V tolerance I/O
ê 100-pins Plastic Quad Flat Package.
ADMtek Incorporate
00/04/25
1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu Tel : (03)578-8879 Fax : (03)578-8871
Version : 1.10
ADMtek Incorporated Confidential






ADM6308 Datasheet, Funktion
Olive plus Specification
6
MDC
43 O Management Data Clock. Provides the reference clock for the MDIO signal
8ma
MDIO
45 BI Management Data Input/output. This pin provides the channels for ADM6308 and
8ma Transceivers to transfer the control information and status.
LED Display
QFLED#
46
High Priority Frame
tri Buffer Full or Faulty LED Display. This occurs when the packet is lost and flow control is
8ma disabled. Or, if flow control is enabled and jam or PAUSE frames are sent, buffer full LED
will flash. If it is found faulty, the LED will always be on. (See LED function description)
high_port[0]
high_port[1]
high_port[2]
high_port[3]
high_port[4]
high_port[5]
high_port[6]
high_port[7]
53 BI Priority setting for port0~port7. Internally pull down.
54 High = high priority
55
56
58
59
60
61
Configuration
BP0 50
BP1 49
NA16#
XFC#
51
48
Miscellaneous
I Back Pressure Mode. Internally pull down. The BP0~1 modes define 4 different back-
pressure methods. Each BPA1~3 has different algorithm described in EEPROM section.
The following shows ADM6308 configuration of back-pressure.
BP1 BP0
0 0 Back Pressure Disable
0 1 BPA1 (Back Pressure Algorithm 1) Enable
1 0 BPA2 (Back Pressure Algorithm 2) Enable
1 1 BPA3 (Back Pressure Algorithm 3) Enable
I Not aborted after continuous 16- times of collision if pull down. Internally pull up.
I Full Duplex Flow Control. Internally pull up. When 802.3 x flow control is disable, no
PAUSE frame will be sent. (default)
REFCLK
RESET#
RECALL
TEST[0]
TEST[1]
Power
10 I Clock reference input of 50MHz Reduced MII. Synchronous clock reference for receiving,
transmitting, and control interface.
63 I RESET#. Active low. For power on reset to initiate ADM6308 and let all the state machines
and statuses enter the initial and default state. Besides, all the LED will be turned on when
power is on or RAM testing failed.
52 I Whenever the level is changed, ADM6308 recalls EEPROM or 8051-like controller to get
configuration data. Internally pull down.
65 I Test mode. Internally pull down
66 I Test mode. Internally pull down
Vddi
Vddo
6, 23, 38, 57, 68, 89
11, 27, 44, 71, 94
2.5V
3.3V
ADMtek Incorporated
00/04/25
1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu
Version : 1.10
Tel : (03)578-8879 Fax : (03)578-8871
ADMtek Incorporated Confidential

6 Page









ADM6308 pdf, datenblatt
Olive plus Specification
12
2. The configuration can be changed without a reset. Toggling the “recall” pin will read the EEPROM again, while 8051 will
emulate the signal like EEPROM
Operation Modes
Reduced MII interface to PHYs or transceivers can operate at 10/100Mbps full or half-duplex mode. To keep a consistent
operation speed, these two parts (PHY and switching controller) will be automatically adjusted the mode through MDC/MDIO
pins. ADM6308 also provides fixed speed and operation mode configured by EEPROM, and dynamic configuration by the
controller like 8051. All modes support full wire speed operations without any interference.
Automatic Address Learning, Forwarding, and Filtering Function
Address Recognition
ADM6308 provides 1Kbytes embedded MAC address table to implement the address recognition. Self-learning bridge
function is based on source address packets field. Look-up table and two different hashing algorithms strengthen the
bridge ability with high performance assurance. Configurable aging time is also supported. An entry of hashing table is
calculated by 32-bit polynomial (called CRC hashing function) or direct mapping (called simple hashing function), as well
as MAC address (called input data). Direct mapping function is allocated the lowest 10 bits of SA/DA address as buffer
address entry. Hashing function selection is set to bit 13 of offset 01H in EEPROM. Each DA (Destination Address)
passes through hashing function and gets a 10-bit entry point of embedded SRAM. If the record is empty, the packet is
broadcast, treated as an unknown frame. Otherwise, the record is read, then MAC address in storage and DA from current
packet are compared. If the two addresses are the same, a port number is decided, and the packet is forwarded to the
assigned port. If the two addresses are different, the incoming packet is also treated as an unknown packet. A broadcast
packet will pass through the other ports without address recognition.
Learning Process
Address learning process is composed of SA packets and a hashing function described above. For each incoming packet,
ADM6308 will check and see whether the packet is errorless and whether the content of the entry address in SRAM is
assigned. If it is, the packet will be compared to source MAC address, and the port number. If both fields match the packet
information, aging status is revised to new learnt address. If MAC addresses matches, but the port number is different, port
number is re-assigned. When the entry collides, the new SA address is ignored and the record keeps the old one. Last
possibility, if the record is free, MAC address and port number of the incoming packet are stored. The following diagram
describes the general operations of address learning and recognition.
DA or SA
CRC or Direct Mapping
Hashing Function
[0:9]
Address
Entry Point
AAA-1
AAA
AAA+1
Address Look-up Table
Fig. 1 Address Learning and Recognition
Forwarding Scheme
ADM6308 forwarding scheme adopts store-and-forward method. Each determined outgoing packet in the buffer of
incoming port is directly sent to the assigned port. The forwarding scheme of unknown packets is treated the same as
broadcast packet. ADM6308 also requires first- in-first-out service, to prevent packets disorder.
IEEE 802.3 Congestion Control
In half duplex operation, ADM6308 supports back pressure feature. When the buffer is full, jam packet or 802.3x control
frame is sent to the connected segment, which is called back - pressure.
ADM6308 implements Alternative back - pressure based on either one of three algorithms described in EEPROM section. If
free blocks in the buffer memory match or are below the threshold, jam packet is directly transmitted regardless of routing
decision.
ADMtek Incorporated
00/04/25
1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu
Version : 1.10
Tel : (03)578-8879 Fax : (03)578-8871
ADMtek Incorporated Confidential

12 Page





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