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ADG821 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG821
Beschreibung Dual SPST Switches
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADG821 Datasheet, Funktion
a
FEATURES
0.8 Max On Resistance @125؇C
0.28 Max On Resistance Flatness @125؇C
1.8 V to 5.5 V Single Supply
200 mA Current Carrying Capability
Automotive Temperature Range: –40؇C to +125؇C
Rail-to-Rail Operation
8-Lead MSOP Package
33 ns Switching Times
Typical Power Consumption (<0.01 W)
TTL/CMOS Compatible Inputs
Pin Compatible with ADG721/722/723
APPLICATIONS
Power Routing
Battery-Powered Systems
Communication Systems
Data Acquisition Systems
Audio and Video Signal Routing
Cellular Phones
Modems
PCMCIA Cards
Hard Drives
Relay Replacement
<1 CMOS 1.8 V to 5.5 V,
Dual SPST Switches
ADG821/ADG822/ADG823
FUNCTIONAL BLOCK DIAGRAM
ADG821
ADG822
S1 S1
IN1 IN1
D1 D1
D2 D2
IN2 IN2
S2 S2
ADG823
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC “0”
INPUT
GENERAL DESCRIPTION
The ADG821, ADG822, and ADG823 are monolithic CMOS
SPST (single pole, single throw) switches. These switches are
designed on an advanced submicron process that provides low
power dissipation, yet gives high switching speed, low on
resistance, and low leakage currents.
The ADG821, ADG822, and ADG823 are designed to operate
from a single 1.8 V to 5.5 V supply, making them ideal for use
in battery-powered instruments.
Each switch of the ADG821/ADG822/ADG823 conducts equally
well in both directions when on. The ADG821, ADG822, and
ADG823 contain two independent SPST switches. The ADG821
and ADG822 differ only in that both switches are normally open
and normally closed, respectively. In the ADG823, Switch 1 is
normally open and Switch 2 is normally closed. The ADG823
exhibits break-before-make switching action.
The ADG821, ADG822, and ADG823 are available in an 8-lead
MSOP package.
PRODUCT HIGHLIGHTS
1. Very Low On Resistance (0.5 typ)
2. On Resistance Flatness (RFLAT(ON)) (0.15 typ)
3. Automotive Temperature Range –40°C to +125°C
4. 200 mA Current Carrying Capability
5. Low Power Dissipation. CMOS construction ensures low
power dissipation.
6. 8-Lead MSOP Package
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






ADG821 Datasheet, Funktion
ADG821/ADG822/ADG823–Typical Performance Characteristics
0.8
0.7 VDD = 3.0V VDD = 2.7V
TA = 25؇C
0.6 VDD = 3.3V
0.5
VDD = 4.5V
0.4
0.3
VDD = 5.0V
0.2 VDD = 5.5V
0.1
0
0 1 2 3 4 55
VD (VS) – V
TPC 1. On Resistance vs. VD (VS)
5.0
4.5 TA = 25؇C
4.0
3.5 VDD = 1.8V
3.0
2.5
2.0
1.5
1.0
0.5
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VD (VS) – V
TPC 2. On Resistance vs. VD (VS)
0.8
VDD = 5V
0.7
0.6
0.5
+125؇C
+85؇C
0.4
0.3
0.2
+25؇C
0.1 –40؇C
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VD (VS) – V
TPC 3. On Resistance vs. VD (VS)
for Different Temperatures
0.8
0.7
+125؇C
0.6 +85؇C
0.5
0.4
0.3
0.2
+25؇C
–40؇C
0.1
VDD = 3V
0
0 0.5 1.0 1.5 2.0 2.5 3.0
VD (VS) – V
TPC 4. On Resistance vs. VD (VS)
for Different Temperatures
8
7 VDD = 5V, 3V
6
5 IS, ID (ON)
4
3 ID (OFF)
2
1
0 IS (OFF)
–1
0 20 40 60 80 100 120 125
TEMPERATURE – ؇C
TPC 5. Leakage Currents vs.
Temperature
200
TA = 25؇C
150
VDD = 5V
100
50
VDD = 3V
0
–50
–100
–150
–200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vs – V
TPC 6. Charge Injection vs.
Source Voltage
60
TA = 25؇C
50 VDD = 3V
40
tON
30
VDD = 5V
20
tOFF
10
VDD = 3V, 5V
0
–40 –20
0 20 40 60 80 100 1200
TEMPERATURE – ؇C
TPC 7. tON/tOFF vs. Temperature
0
VDD = 3V, 5V
–10 TA = 25؇C
–20
–30
–40
–50
–60
–70
0.2
1 10
FREQUENCY – MHz
100
TPC 8. Off Isolation vs. Frequency
0
–1
–2
–3
–4
–5
–6
–7
–8 VDD = 3V, 5V
TA = 25؇C
–9
0.1 1 10
FREQUENCY – MHz
100
TPC 9. On Response vs. Frequency
–6– REV. 0

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