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ADV7152 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7152
Beschreibung CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 32 Seiten
ADV7152 Datasheet, Funktion
a
CMOS 220 MHz True-Color Graphics
Triple 10-Bit Video RAM-DAC
ADV7152
FEATURES
APPLICATIONS
220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color
High Resolution, True Color Graphics
Triple 10-Bit “Gamma Correcting” D/A Converters
Professional Color Prepress Imaging
Triple 256 ؋ 10 (256 ؋ 30) Color Palette RAM
On-Chip Clock Control Circuit
GENERAL DESCRIPTION
Palette Priority Select Registers
The ADV7152 (ADV®) is a complete analog output, Video
RS-343A/RS-170 Compatible Analog Outputs
RAM-DAC on a single CMOS monolithic chip. The part is spe-
TTL Compatible Digital Inputs
cifically designed for use in high performance, color graphics
Standard MPU l/O Interface
workstations. The ADV7152 integrates a number of graphic
10-Bit Parallel Structure
functions onto one device allowing 24-bit direct True-Color op-
8+2 Byte Structure
eration at the maximum screen update rate of 220 MHz. The
Programmable Pixel Port: 24-Bit and 8-Bit (Pseudo)
ADV7152 implements 30-bit True Color in 24-bit frame buffer
Pixel Data Serializer
designs. The part also supports other modes, including 15-bit
Multiplexed Pixel Input Ports; 1:1, 2:1
True Color and 8-bit Pseudo or Indexed Color. Either the Red,
+5 V CMOS Monolithic Construction
Green or Blue input pixel ports can be used for Pseudo Color.
100-Lead Plastic Quad Flatpack (QFP)
Thermally Enhanced to Achieve JC < 1.0؇C/W
The device consists of three, high speed, 10-bit, video D/A con-
verters (RGB), three 256 ϫ 10 (one 256 ϫ 30) color look-up
MODES OF OPERATION
tables, palette priority selects, a pixel input data multiplexer/
24-Bit True Color (30-Bit Gamma Corrected)
serializer and a clock generator/divider circuit. The ADV7152
@ 220 MHz
implements 1:1 and 2:1 pixel data multiplexing. The onboard
@ 170 MHz
palette priority select inputs enable multiple palette devices to
@ 135 MHz
be connected together for use in multipalette and window
@ 110 MHz
(Continued on page 10)
@ 85 MHz
8-Bit Pseudo Color
ADV is a registered trademark of Analog Devices, Inc.
15-Bit True Color
FUNCTIONAL BLOCK DIAGRAM
VAA
256-COLOR/GAMMA
PALETTE RAM
ADV7152
RED (R0–R7),
GREEN (G0–G7),
BLUE (B0–B7)
COLOR DATA
A
B
PALETTE
SELECTS
(PS0, PS1)
LOADIN
LOADOUT
PRGCKOUT
SCKIN
SCKOUT
SYNC
BLANK
CLOCK
CLOCK
24
P 48
I
X
24 E
MUX
2:1
L
P
O
4
R
T
4
MUX
2:1
8
8
8
2
CLOCK CONTROL
CLOCK DIVIDE
&
SYNCHRONIZATION
CIRCUIT
÷32, ÷16, ÷8, ÷4, ÷2
ADDRESS
REGISTER
ADDR
(A0-–A15)
MODE
REGISTER
(MR1)
ECL TO CMOS
RED
256 x 10
GREEN
256 x 10
10
10
BLUE
256 x 10
10
10-BIT
RED DAC
10-BIT
GREEN DAC
10-BIT
BLUE DAC
CONTROL REGISTERS
PIXEL MASK
REGISTER
TEST
REGISTERS
COMMAND
REGISTERS
(CR1-CR3)
ID
REGISTER
REVISION
REGISTER
SYNC
OUTPUT
DATA TO
PALETTES
VOLTAGE
REFERENCE
CIRCUIT
30 COLOR REGISTERS
RED
GREEN
BLUE
REGISTER REGISTER REGISTER
MPU PORT
10 (8+2)
IOR
IOR
IOG
IOG
IOB
IOB
IPLL
SYNCOUT
VREF
RSET
COMP
REV. B
CE R/W C0 C1
D9 – D0
GND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADV7152 Datasheet, Funktion
ADV7152
SCKIN
t13
BLANK
t14
t15
BLANKING PERIOD
SCKOUT
END OF SCAN
LINE (N)
START OF SCAN
LINE (N+1)
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 7. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)
CLOCK
ANALOG
OUTPUTS
IOR, IOR
IOG, IOG
IOB, IOB
IPLL , SYNCOUT
t16
t18
WHITE LEVEL
90 %
50 %
FULL SCALE
TRANSITION
R/W, C0, C1
CE
D0–D9
(READ MODE)
D0–D9
(WRITE MODE)
10 %
BLACK LEVEL
t17
NOTE:
THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY,
THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND
AMPLITUDE W.R.T. THE CLOCK WAVEFORM.
IPLL AND SYNCOUT ARE DIGITAL OUTPUT SIGNALS. t16 IS THE ONLY
RELEVANT OUTPUT TIMING SPECIFICATION FOR IPLL AND SYNCOUT.
Figure 8. Analog Output Response vs. CLOCK
t19 t20
VALID
CONTROL DATA
t21
t24
t23
R/W = 1
t22
t25
R/W = 0
t26
t27
Figure 9. Microprocessor Port (MPU) Interface Timing
–6– REV. B

6 Page









ADV7152 pdf, datenblatt
ADV7152
Alternatively, the ADV7152 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 13), such as the
ICS1562. The ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
LOW FREQUENCY
OSCILLATOR
GND
VCLOCK
ECLOUT+
+5V ECLOUT–
VCC
VCC
220
220
330
330
VAA
+5V
CLOCK
CLOCK
CLOCK
GENERATOR
VREF OUT
GND
GND
VAA
0.1 µF
ADV7152
VREF
GND
D0–D3 CS R/W
GND
Figure 13. PLL Generator Driving CLOCK, CLOCK of the
ADV7152
CLOCK CONTROL SIGNALS LOADOUT
The ADV7152 generates a LOADOUT control signal which
runs at a divided down frequency of the pixel CLOCK. The
frequency is automatically set to the programmed multiplex
rate, controlled by CR36 of Command Register 3.
fLOADOUT = fCLOCK/2
fLOADOUT = fCLOCK
2:1 Multiplex Mode
1:1 Multiplex Mode
The LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7152. This is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT.
VIDEO
FRAME
BUFFER
LOADOUT
ADV7152
LOADIN
PIXEL
DATA
LOADOUT(1)
LOADOUT
VIDEO
FRAME
BUFFER LOADOUT(2)
ADV7152
LOADIN
PIXEL
DATA
LOADOUT
LOADIN
LOADOUT(1)
LOADOUT(2)
DELAY
Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT(1) and LOADOUT(2)).
LOADIN and Pixel Data must conform to the setup and hold
times (t8 and t9).
If however, it is required that the ADV7152 has a fixed number
of pipeline delays (tPD), LOADOUT and LOADIN must con-
form to timing specifications t10 and τ-t11 as illustrated in Fig-
ures 4 and 5.
PRGCKOUT
The PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 8). The rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT
fPRGCKOUT = f CLOCK/N
where N = 4, 8, 16 or 32.
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCKIN, SCKOUT
These video memory signals are used to minimize external sup-
port chips. Figure 15 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). The resulting signal is
output on SCKOUT. Figure 7 of the Timing Waveform section
shows the relationship between SCKOUT, SCKIN and
BLANK.
SCKOUT
BLANK
SYNC
SCKIN
LATCH
ENABLE
Figure 15. SCKOUT Generation Circuit
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 16
shows a suggested frame buffer to ADV7152 interface. This is a
minimum chip solution and allows the ADV7152 control the
overall graphics system clocking and synchronization.
VIDEO
FRAME
BUFFER
LOADOUT
LOADIN
SCKIN
ADV7152
BLANK
SCKOUT
PIXEL
DATA
Figure 16. ADV7152 Interface Using SCKIN and SCKOUT
–12–
REV. B

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