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ADV7121 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7121
Beschreibung CMOS 80 MHz/ Triple 10-Bit Video DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADV7121 Datasheet, Funktion
a
CMOS
80 MHz, Triple 10-Bit Video DACs
ADV7121/ADV7122
FEATURES
80 MHz Pipelined Operation
Triple 10-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP Package (ADV7121)
44-Pin PLCC Package (ADV7122)
48-Lead TQFP (ADV7122)
APPLICATIONS
High Definition Television (HDTV)
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Direct Digital Synthesis (DDS)
I/Q Modulation
SPEED GRADES
80 MHz
50 MHz
30 MHz
GENERAL DESCRIPTION
The ADV7121/ADV7122 (ADV®) is a video speed, digital-to-
analog converter on a single monolithic chip. The part is specifi-
cally designed for high resolution color graphics and video
systems including high definition television (HDTV). It is also
ideal for any application requiring a low cost, high speed DAC
function especially in communications. It consists of three, high
speed, 10-bit, video D/A converters (RGB), a standard TTL input
interface and high impedance, analog output, current sources.
The ADV7121/ADV7122 has three separate, 10-bit, pixel input
ports, one each for red, green and blue video data. A single +5 V
power supply, an external 1.23 V reference and pixel clock input is
all that is required to make the part operational. The ADV7122
has additional video control signals, composite SYNC and BLANK.
The ADV7121/ADV7122 is capable of generating RGB video
output signals which are compatible with RS-343A, RS-170 and
most proposed production system HDTV video standards, in-
cluding SMPTE 240M.
The ADV7121/ADV7122 is fabricated in a +5 V CMOS pro-
cess. Its monolithic CMOS construction ensures greater func-
tionality with low power dissipation. The ADV7121 is packaged
in a 0.6", 40-pin plastic DIP package. The ADV7122 is pack-
ADV is a registered trademark of Analog Devices, Inc.
*Speed grades up to 140 MHz are also available on special request.
Please contact Analog Devices or its representatives for details.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADV7121 FUNCTIONAL BLOCK DIAGRAM
FS
VAA ADJUST VREF
CLOCK
ADV7121
REFERENCE
AMPLIFIER
COMP
R0
R9
PIXEL
INPUT
PORT
G0
G9
B0
B9
RED
10
10 REGISTER
GREEN 10
10 REGISTER
BLUE
10
10 REGISTER
DAC
DAC
DAC
IOR
IOG
IOB
GND
ADV7122 FUNCTIONAL BLOCK DIAGRAM
FS
VAA ADJUST VREF
CLOCK
ADV7122
REFERENCE
AMPLIFIER
COMP
R0
R9
PIXEL
INPUT
PORT
G0
G9
B0
B9
RED 10
10 REGISTER
GREEN 10
10 REGISTER
BLUE 10
10 REGISTER
DAC
DAC
DAC
IOR
IOG
IOB
BLANK
SYNC
CONTROL
REGISTER
SYNC
CONTROL
GND
aged in a 44-pin plastic leaded (J-lead) chip carrier, PLCC,
and 48-lead thin quad flatpack (TQFP).
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz.
2. Guaranteed monotonic to 10 bits. Ten bits of resolution al-
lows for implementation of linearization functions such as
gamma correction and contrast enhancement.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A/RS-170 and the pro-
posed SMPTE 240M standard for HDTV.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADV7121 Datasheet, Funktion
ADV7121/ADV7122
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK*
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a logical zero, the R0–R9, G0–G9 and R0–R9 pixel inputs are ignored.
SYNC*
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE
current source. This is internally connected to the IOG analog output. SYNC does not override any other
control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the
rising edge of CLOCK.
If sync information is not required on the green channel, the SYNC input should be tied to logical zero.
CLOCK
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated TTL buffer.
R0–R9,
G0–G9,
B0–B9
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
IOR, IOG, IOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.
FS ADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG)
is given by:
RSET ()
= 12,082 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG and IOB is given by:
IOG* (mA)
IOR, IOB (mA)
= 12,082 × VREF (V)/RSET () (SYNC being asserted)
= 8,628 × VREF (V)/RSET ()
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e., SYNC
tied permanently low. For the ADV7121, all three analog output currents are as described by:
COMP
VREF
VAA
GND
IOR, IOG, IOB (mA)
= 7,969 × VREF (V)/RSET ()
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor
must be connected between COMP and VAA.
Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an
external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be
connected between VREF and VAA.
Analog power supply (5 V ± 5%). All VAA pins on the ADV7121/ADV7122 must be connected.
Ground. All GND pins must be connected.
*SYNC and BLANK functions are not provided on the ADV7121.
–6– REV. B

6 Page









ADV7121 pdf, datenblatt
ADV7121/ADV7122
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Terminal Plastic Leaded Chip Carrier
(P-44A)
40-Pin Plastic DIP
(N-40A)
–12–
REV. B

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