ADV476 Datasheet PDF - Analog Devices
| Part Number | ADV476 | |
| Description | CMOS Monolithic 256x18 Color Palette RAM-DAC | |
| Manufacturers | Analog Devices | |
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a
CMOS Monolithic 256؋18
Color Palette RAM-DAC
ADV476
FEATURES
Personal System/2* and VGA* Compatible
Plug-in Replacement for INMOS 171/176
66 MHz Pipelined Operation
Three 6-Bit D/A Converters
256؋18 Color Palette RAM
RS-343A/RS-170 Compatible Outputs
Blank on All Three Channels
Standard MPU Interface
Asynchronous Access to All Internal Registers
؉5 V CMOS Monolithic Construction
Low Power Dissipation
Standard 28-Pin, 0.6" DIP and 44-Pin PLCC
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
50 MHz
35 MHz
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADV476 (ADV®) is a pin compatible and software compat-
ible RAM-DAC designed specifically for VGA and Personal
System/2 color graphics.
The ADV476 is a complete analog output RAM-DAC on a
single monolithic chip. The part contains a 256ϫ18 color
lookup table, a pixel mask register as well as a triple 6-bit video
D/A converter. The ADV476 is capable of simultaneously dis-
playing up to 256 colors, from a total color palette of 262,144
addressable colors.
The on-chip asynchronous MPU bus allows access to the color
lookup table without affecting the input video data via the pixel
port. The pixel read mask register provides a convenient way of
altering the displayed colors without updating the color lookup
table. The ADV476 is capable of generating RGB video output
signals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV476 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation and small board area. The part is packaged in
a 0.6", 28-pin DIP and a 44-pin PLCC.
PRODUCT HIGHLIGHTS
1. Standard video refresh rates, 35 MHz, 50 MHz and
66 MHz.
2. Fully compatible with VGA and Personal System/2 color
graphics.
3. Guaranteed monotonic. Integral and differential linearity
guaranteed to be a maximum of ± 1 LSB.
4. Low glitch energy, 75 pV secs.
*Personal System/2 and VGA are trademarks of International Business
Machines Corp.
ADV is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
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ADV476
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
PCLK
P0–P7
RED, GREEN,
BLUE
VCC
GND
IREF
WR
RD
RS0, RS1
D0–D7
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs to
the blanking level, as shown in Table V. The BLANK signal is latched on the rising edge of PCLK. While
BLANK is a logical zero, the pixel inputs are ignored.
Clock input (TTL compatible). The rising edge of PCLK latches the P0–P7 data inputs and the BLANK control
input. It is typically the pixel clock rate of the video system. PCLK should be driven by a dedicated TTL buffer.
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. P0–P7 pixel select inputs are latched on the rising
edge of PCLK. P0 is the LSB. Unused pixel select inputs should be connected to GND.
Red, green and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable, as shown in Figure 4a. All three current outputs should have similar out-
put loads whether or not they are all being used.
Analog power supply (5 V ± 10%).
Analog ground.
Current reference input. The relationship between the current input and the full scale output voltage of the
DACs is given by the following expression:
IREF = VO (Full Scale)/2.15 ϫ RL
RL = Load Resistance
Write control input (TTL compatible). WR must be at logical zero when writing data to the device. D0–D7 data
is latched on the rising edge of WR. See Figure 1.
Read control input (TTL compatible). RD must both be at logical zero when reading data from the device.
See Figure 1.
Command control inputs (TTL compatible). RS0 and RS1 specify the type of read or write operation being car-
ried out, i.e., address register or color palette RAM read or write operations. See Tables I, II, III.
Data bus (TTL compatible). Data is transferred to and from the address register and the color palette RAM over
this 8-bit bidirectional data bus. D0 is the least significant bit.
TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the Video portion
of the waveform. Usually referred to as the Front Porch or Back
Porch. At 0 IRE Units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)
This usually refers to the technique of combining the three pri-
mary colors of Red, Green and Blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Gray Scale
The discrete levels of video signal between Reference Black and
Reference White levels. An 8-bit DAC contains 256 different
levels while a 6-bit DAC contains 64.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between Reference White and Reference Black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
REV. B
–5–
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| Information | Total 12 Pages | |
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| Download | [ ADV476.PDF Datasheet ] | |
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